| V1 |
|
0.00% |
| V2 |
|
50.00% |
| V2S |
|
45.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| kmac_smoke | 11.873s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| kmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| kmac_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| kmac_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| kmac_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 0 | 1 | 0.00 | |||
| kmac_long_msg_and_output | 60.238s | 0.000us | 0 | 1 | 0.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 98.440s | 0.000us | 1 | 1 | 100.00 | |
| test_vectors | 6 | 8 | 75.00 | |||
| kmac_test_vectors_sha3_224 | 13.899s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_256 | 1418.390s | 0.000us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 56.290s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_512 | 11.890s | 0.000us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 97.110s | 0.000us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 1244.060s | 0.000us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 1.690s | 0.000us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 1.370s | 0.000us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 219.530s | 0.000us | 1 | 1 | 100.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 38.394s | 0.000us | 0 | 1 | 0.00 | |
| app_with_partial_data | 1 | 1 | 100.00 | |||
| kmac_app_with_partial_data | 82.710s | 0.000us | 1 | 1 | 100.00 | |
| entropy_refresh | 1 | 1 | 100.00 | |||
| kmac_entropy_refresh | 21.230s | 0.000us | 1 | 1 | 100.00 | |
| error | 1 | 1 | 100.00 | |||
| kmac_error | 123.470s | 0.000us | 1 | 1 | 100.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 36.281s | 0.000us | 0 | 1 | 0.00 | |
| sideload_invalid | 1 | 1 | 100.00 | |||
| kmac_sideload_invalid | 0.850s | 0.000us | 1 | 1 | 100.00 | |
| edn_timeout_error | 1 | 1 | 100.00 | |||
| kmac_edn_timeout_error | 5.730s | 0.000us | 1 | 1 | 100.00 | |
| entropy_mode_error | 0 | 1 | 0.00 | |||
| kmac_entropy_mode_error | 34.251s | 0.000us | 0 | 1 | 0.00 | |
| entropy_ready_error | 1 | 1 | 100.00 | |||
| kmac_entropy_ready_error | 31.920s | 0.000us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 0.890s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| kmac_stress_all | 1139.400s | 0.000us | 1 | 1 | 100.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| kmac_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.650s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| kmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| kmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| kmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| kmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| kmac_sec_cm | 17.400s | 0.000us | 1 | 1 | 100.00 | |
| kmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| kmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 0.890s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_sw_key_key_masking | 0 | 1 | 0.00 | |||
| kmac_smoke | 11.873s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 219.530s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 17.400s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 17.400s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_packer_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 17.400s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 0 | 1 | 0.00 | |||
| kmac_smoke | 11.873s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_global_esc | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 0.890s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_fsm_local_esc | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 17.400s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 1 | 1 | 100.00 | |||
| kmac_mubi | 192.880s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 0 | 1 | 0.00 | |||
| kmac_smoke | 11.873s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 70.540s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 118 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 19.800 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| kmac_smoke | 94075959844496733318305304441080702968723340252865107818131510914002212253744 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_long_msg_and_output | 50636451574589102332027723333662712175075607105901592957866498009552030869404 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_test_vectors_sha3_224 | 101040487493219753057328610613255635029473832919286254917459454656796991472404 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_test_vectors_sha3_384 | 61021451328518585587894126960226416753662540485588921758494765937155792859121 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_app | 94722170699563779835351011312453562500761111998880118165435954060860874971864 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_key_error | 57884206631356053317564119048904185665120686188185781216972707475636907413250 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_entropy_mode_error | 42461157724859783493219807085528695791332495072331549456679739900374090310916 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| kmac_stress_all_with_rand_reset | 44506062642628701481374125809030219842707834521497634636866124424865473407858 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| Job killed most likely because its dependent job failed. | ||||
| kmac_shadow_reg_errors | 10224804934865871628163731113444266194208146970423937509395283306575754799303 | None | ||
| kmac_shadow_reg_errors_with_csr_rw | 40014101643916347531387109776423265861070411412275836568748932229960359292439 | None | ||
| kmac_mem_walk | 58086912254992603934966236538265566629264730964209696663623209848453980567656 | None | ||
| kmac_mem_partial_access | 4073524597666023447229140180461980493868332821813462528701066568257079589955 | None | ||
| kmac_tl_errors | 53879894848465092763076999972272125260187394821115962084531653670322248815437 | None | ||
| kmac_tl_intg_err | 34900718507518554580386844687206501028288697553743016090351255249520389895587 | None | ||
| kmac_intr_test | 49544494319586586773463476530963722310145353515133110152043638147245927157049 | None | ||
| kmac_csr_hw_reset | 40374787352217023476126660768861215238303593327493320413472401228357650900446 | None | ||
| kmac_csr_rw | 65386641195019007332100260933272671648046671320069043427860824654719261191326 | None | ||
| kmac_csr_bit_bash | 106412680804506481867373095250518371152729025389824582535719187303609677483094 | None | ||
| kmac_csr_aliasing | 63366284274729422757627228434073743312246411200981741184483260085485956218872 | None | ||
| kmac_same_csr_outstanding | 94574784336549485277538037555683287818796957556757208616749098582022397964947 | None | ||
| kmac_csr_mem_rw_with_rand_reset | 113972312916687585991482030203767993326610976385476845740620426524835903023840 | None | ||