Simulation Results: lc_ctrl/volatile_unlock_disabled

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
62.50%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
lc_ctrl_smoke 36.240s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.950s 0.000us 1 1 100.00
csr_rw 0 1 0.00
lc_ctrl_csr_rw 17.900s 0.000us 0 1 0.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.010s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.920s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
lc_ctrl_csr_rw 17.900s 0.000us 0 1 0.00
lc_ctrl_csr_aliasing 0.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.800s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.970s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.630s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.410s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.930s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_prog_failure 1.410s 0.000us 1 1 100.00
lc_ctrl_errors 3.930s 0.000us 1 1 100.00
lc_ctrl_security_escalation 6.160s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 16.390s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.450s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 12.370s 0.000us 1 1 100.00
jtag_access 11 13 84.62
lc_ctrl_jtag_csr_hw_reset 1.380s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.880s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 16.050s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.050s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 38.319s 0.000us 0 1 0.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 13.836s 0.000us 0 1 0.00
lc_ctrl_jtag_alert_test 1.320s 0.000us 1 1 100.00
lc_ctrl_jtag_smoke 2.620s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.160s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.450s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 12.370s 0.000us 1 1 100.00
lc_ctrl_jtag_access 2.200s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.240s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.510s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.730s 0.000us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 9.929s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.700s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.590s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.590s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
lc_ctrl_csr_hw_reset 0.950s 0.000us 1 1 100.00
lc_ctrl_csr_rw 17.900s 0.000us 0 1 0.00
lc_ctrl_csr_aliasing 0.980s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
lc_ctrl_csr_hw_reset 0.950s 0.000us 1 1 100.00
lc_ctrl_csr_rw 17.900s 0.000us 0 1 0.00
lc_ctrl_csr_aliasing 0.980s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
lc_ctrl_tl_intg_err 1.490s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.490s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.970s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 8.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 39.920s 0.000us 0 1 0.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.160s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.800s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.160s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.350s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.350s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.230s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.990s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.900s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
lc_ctrl_jtag_same_csr_outstanding 110879740711356024470498283560789737565190455606740003745396117881892992163758 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 104542023198013401106174851485229658794676843016328547859211312819252602657715 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_csr_rw 56184791846002292191120437204058371325927436983010529391538588304248607997329 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:44 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_smoke 81787235677041742575928377104605171749629157651293597292090595336196275734743 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:44 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_stress_all 64326718700319093548122269325929915864117370679418081145140527370596627959297 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:44 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_sec_cm 5485009723867228200766698748911485370515225791576195016170840136258450312814 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:44 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl None None
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-merge_across_libs needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 79287183406588742979447872771158678934348757714217450022516212752447556799916 2472
UVM_ERROR @ 12734146881 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12734146881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed.
lc_ctrl None None