Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.66 %
  • code
  • 81.67 %
  • assert
  • 95.99 %
  • func
  • 88.31 %
  • line
  • 97.66 %
  • branch
  • 96.01 %
  • cond
  • 78.04 %
  • toggle
  • 87.55 %
  • FSM
  • 49.09 %
Validation stages
V1
100.00%
V2
90.00%
V2S
92.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.430s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.050s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.120s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 13.873s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.120s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.660s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.140s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.310s 0.000us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_prog_failure 2.140s 0.000us 1 1 100.00
lc_ctrl_errors 6.310s 0.000us 1 1 100.00
lc_ctrl_security_escalation 36.303s 0.000us 0 1 0.00
lc_ctrl_jtag_state_failure 15.640s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.290s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 14.020s 0.000us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.420s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 34.245s 0.000us 0 1 0.00
lc_ctrl_jtag_csr_bit_bash 9.000s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.570s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.950s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.030s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.620s 0.000us 1 1 100.00
lc_ctrl_jtag_smoke 5.520s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.790s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.290s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 14.020s 0.000us 1 1 100.00
lc_ctrl_jtag_access 7.000s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.980s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.540s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 32.700s 0.000us 1 1 100.00
alert_test 0 1 0.00
lc_ctrl_alert_test 11.951s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.180s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.180s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.760s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.760s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.080s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.080s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.120s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.340s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.600s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
lc_ctrl_security_escalation 36.303s 0.000us 0 1 0.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 13.873s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 7.790s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.870s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.870s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.520s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.470s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.470s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.350s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
lc_ctrl_jtag_csr_rw 56719719188281223980618762571803785895098071828515003293290091326368516075258 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_state_post_trans 81728222117622550819243755656571499335501345733797281479994959458278734771763 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:45 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_security_escalation 71466133018338049888959940833532260023013820604962427564430538244341399017473 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:45 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_alert_test 77887029864901780905675592318825284321934188696873022392546297566941793867134 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:45 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 12035126885026265799351092911511565499671787329295898407745238941271925030763 838
UVM_ERROR @ 846216612 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 846216612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---