| V1 |
|
72.73% |
| V2 |
|
44.00% |
| V2S |
|
3.57% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 0 | 1 | 0.00 | |||
| otp_ctrl_wake_up | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| smoke | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 2.330s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_rw | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 7.140s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_aliasing | 7.790s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 3.050s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otp_ctrl_csr_rw | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.790s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_walk | 62.348s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otp_ctrl_mem_partial_access | 1.290s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_partition_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| init_fail | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partition_check | 0 | 2 | 0.00 | |||
| otp_ctrl_background_chks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_check_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_during_otp_init | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partition_lock | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interface_key_check | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_key_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_interactions | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_dai_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_macro_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_access | 0 | 1 | 0.00 | |||
| otp_ctrl_test_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otp_ctrl_intr_test | 1.830s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| otp_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_errors | 3.480s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_errors | 3.480s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 2.330s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.790s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 3.110s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 2.330s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.790s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 3.110s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otp_ctrl_tl_intg_err | 20.070s | 0.000us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_intg_err | 20.070s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_secret_mem_scramble | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_digest | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_seed_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_entropy_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_integ_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_cnsty_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_lfsr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_bkgn_chk | 0 | 1 | 0.00 | |||
| otp_ctrl_check_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_regren | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unreadable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unwritable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_access_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_test_bus_lc_gated | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_direct_access_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_check_trigger_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_check_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_macro_mem_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 0 | 1 | 0.00 | |||
| otp_ctrl_low_freq_read | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | ||||
| default | None | None |
Job timed out after 60 minutes
|
|
| Job returned non-zero exit code | ||||
| otp_ctrl_mem_walk | 96908347602708575437360821663919137342363931996741977165810123667806053194747 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:39 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| otp_ctrl | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| otp_ctrl_wake_up | 52216346424385954656486273086056432512605949111611687796650260842552577722087 | None | ||
| otp_ctrl_smoke | 39274147150455392732516098979931474273758534864951528632548376942650537133847 | None | ||
| otp_ctrl_partition_walk | 104874944584466448938674924206573079975224897392360225280827962429188810515215 | None | ||
| otp_ctrl_low_freq_read | 37413480752562173639943648783589252528042224189580025122956390001549542133970 | None | ||
| otp_ctrl_init_fail | 4489443349536954399218385952229643739287136569111540331766025995117799865115 | None | ||
| otp_ctrl_background_chks | 43225062294571022823386341702434185476616444131924827526285371786862006583192 | None | ||
| otp_ctrl_parallel_lc_req | 27170939154973564162339728012579975273866375025108089915464749013008416895033 | None | ||
| otp_ctrl_parallel_lc_esc | 82491999104567591334705076597866342466098788849046813400531537833756553541615 | None | ||
| otp_ctrl_dai_lock | 93209248319114512981853303744094247494882444782101679226280260047391191122279 | None | ||
| otp_ctrl_dai_errs | 78800598257765069542855844808589412745976888352144371680097037786767115042800 | None | ||
| otp_ctrl_check_fail | 105765099672207617647626094317245221547755366272080809835508788020325385818548 | None | ||
| otp_ctrl_macro_errs | 103716126070001414780263802344745036739237294894702878185894728929320060596739 | None | ||
| otp_ctrl_parallel_key_req | 101575173888908969901045391317997314805427709378165058798214260261322950555447 | None | ||
| otp_ctrl_regwen | 58221698751389453824596744495266381178586860145345144515263013543777270172479 | None | ||
| otp_ctrl_test_access | 61908300873391329093954275792267522782119226248579959025068964095515609014993 | None | ||
| otp_ctrl_stress_all_with_rand_reset | 95435893978307143723061036178879581613516471421480345768920028820985790712274 | None | ||
| otp_ctrl_stress_all | 55079742912467656179625058067826219345403377982630716287026451677833431705476 | None | ||
| otp_ctrl_sec_cm | 95769008822596274299316381165906739964523455508755240949205724656660274330087 | None | ||
| otp_ctrl_alert_test | 109839992281967316569283144047668880676141030419542916526139598404769111285612 | None | ||