| V1 |
|
75.00% |
| V2 |
|
75.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_request_test | 3 | 4 | 75.00 | |||
| prim_async_fatal_alert | 0.470s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_alert | 0.450s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.480s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_alert_test | 3 | 4 | 75.00 | |||
| prim_async_fatal_alert | 0.470s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_alert | 0.450s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.480s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_alert_ping_request_test | 3 | 4 | 75.00 | |||
| prim_async_fatal_alert | 0.470s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_alert | 0.450s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.480s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_alert_integrity_errors_test | 3 | 4 | 75.00 | |||
| prim_async_fatal_alert | 0.470s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_alert | 0.450s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.480s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_init_trigger_test | 3 | 4 | 75.00 | |||
| prim_async_fatal_alert | 0.470s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_alert | 0.450s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.480s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| prim_async_fatal_alert_with_3_cycles_skew | 0.410s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module prim_alert_tb
All of 25 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 6.240 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Offending 'ping_ok_o' | ||||
| prim_async_fatal_alert_with_3_cycles_skew | 91666446251997633088119118956057125512522012193915286517870025146755729957426 | 100 |
Offending 'ping_ok_o'
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(312) @ 29623000: reporter [ASSERT FAILED] PingResponse1_A
Starting assertion attempts at time 29653215ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| Job killed most likely because its dependent job failed. | ||||
| prim_async_alert | 28926060057174689029321827409386186298695521594935885104586303733345705639700 | None | ||