Simulation Results: rom_ctrl/32kb

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.96 %
  • code
  • 96.95 %
  • assert
  • 95.49 %
  • func
  • 80.43 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 94.35 %
  • toggle
  • 99.59 %
  • FSM
  • 93.33 %
Validation stages
V1
50.00%
V2
71.43%
V2S
70.83%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.340s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.100s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.930s 0.000us 1 1 100.00
csr_bit_bash 0 1 0.00
rom_ctrl_csr_bit_bash 60.758s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.070s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
rom_ctrl_csr_rw 2.930s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
mem_walk 0 1 0.00
rom_ctrl_mem_walk 32.546s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
rom_ctrl_mem_partial_access 58.250s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 60.633s 0.000us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.250s 0.000us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 36.200s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.430s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.140s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.140s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
rom_ctrl_csr_hw_reset 4.100s 0.000us 1 1 100.00
rom_ctrl_csr_rw 2.930s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 4.090s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
rom_ctrl_csr_hw_reset 4.100s 0.000us 1 1 100.00
rom_ctrl_csr_rw 2.930s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 4.090s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.960s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 11.884s 0.000us 0 1 0.00
rom_ctrl_tl_intg_err 21.410s 0.000us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 11.884s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 11.884s 0.000us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 11.884s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 11.884s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.340s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.340s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.340s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.410s 0.000us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
rom_ctrl_kmac_err_chk 36.200s 0.000us 0 1 0.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.800s 0.000us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.960s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 11.884s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 11.886s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
rom_ctrl_max_throughput_chk 101553381977662735631787878124647815313145286381260799611813603792869460123808 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_kmac_err_chk 70741650046208150439953059544796803743265449577336532416111329676755714920666 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_stress_all_with_rand_reset 92834178795536795713642849547076560429056154149417458773399581305611021616622 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_sec_cm 110738349827969760091325749531559266916335240826683998358809825540719346491085 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:36 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_mem_walk 15130270083929339945932353286895595578644098938384452866218272910297027518897 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:37 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_mem_partial_access 94728850192616846222982831330646989963574441791090720133488507840186331518634 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:37 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_csr_bit_bash 54357962991469722604502344128577693078446631438684285129704508638005940529524 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:37 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
Job timed out after * minutes
rom_ctrl_csr_aliasing 112091660667398503124332312104099827878835669144542358484511369734536190209424 None
Job timed out after 60 minutes