Simulation Results: rstmgr

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
87.50%
V2
42.11%
V2S
36.36%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
rstmgr_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.830s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.750s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 1.960s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.930s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.490s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.750s 0.000us 1 1 100.00
rstmgr_csr_aliasing 0.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 0 1 0.00
rstmgr_por_stretcher 0.000s 0.000us 0 1 0.00
sw_rst 0 1 0.00
rstmgr_sw_rst 0.000s 0.000us 0 1 0.00
sw_rst_reset_race 0 1 0.00
rstmgr_sw_rst_reset_race 0.000s 0.000us 0 1 0.00
reset_info 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
cpu_info 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
alert_info 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
reset_info_capture 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
rstmgr_stress_all 0.000s 0.000us 0 1 0.00
alert_test 0 1 0.00
rstmgr_alert_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.010s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.010s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
rstmgr_csr_hw_reset 0.830s 0.000us 1 1 100.00
rstmgr_csr_rw 0.750s 0.000us 1 1 100.00
rstmgr_csr_aliasing 0.930s 0.000us 1 1 100.00
rstmgr_same_csr_outstanding 37.927s 0.000us 0 1 0.00
tl_d_partial_access 3 4 75.00
rstmgr_csr_hw_reset 0.830s 0.000us 1 1 100.00
rstmgr_csr_rw 0.750s 0.000us 1 1 100.00
rstmgr_csr_aliasing 0.930s 0.000us 1 1 100.00
rstmgr_same_csr_outstanding 37.927s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
rstmgr_tl_intg_err 2.220s 0.000us 1 1 100.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.220s 0.000us 1 1 100.00
sec_cm_scan_intersig_mubi 0 1 0.00
rstmgr_sec_cm_scan_intersig_mubi 0.000s 0.000us 0 1 0.00
sec_cm_leaf_rst_bkgn_chk 0 1 0.00
rstmgr_leaf_rst_cnsty 0.000s 0.000us 0 1 0.00
sec_cm_leaf_rst_shadow 0 1 0.00
rstmgr_leaf_rst_shadow_attack 0.000s 0.000us 0 1 0.00
sec_cm_leaf_fsm_sparse 0 1 0.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.750s 0.000us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.750s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
default None None
recompiling module rstmgr_cov_bind
All of 93 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 15.524 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
rstmgr_same_csr_outstanding 40267465037965585996418409153438949305772466016094164924009138436986474088775 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:34 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rstmgr None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
Job killed most likely because its dependent job failed.
rstmgr_smoke 109205836346148720604882258029655523248375599149964137816649836071815982992690 None
rstmgr_por_stretcher 22097363368066234752019641120732759040529324620069511258004263812242229973326 None
rstmgr_reset 66321026758963264329590665976168988643595894642917455492696323492647591192712 None
rstmgr_sw_rst_reset_race 78421550176118552794156920259396540329969591124732400154353793521027089860782 None
rstmgr_sw_rst 59770825835766107496987684286699088212040407708799146274853913669915848654413 None
rstmgr_sec_cm_scan_intersig_mubi 25994564318567174814919864221762428727260775592197271986461002199289441486799 None
rstmgr_leaf_rst_cnsty 59108590805318754050786554635743871293327514675632210374384744453540162481188 None
rstmgr_leaf_rst_shadow_attack 39280723548100775966415226483142958195202766565960452283895586634957319778727 None
rstmgr_stress_all 24302680241085266864687844170807176848438704106659468471622707291781778652249 None
rstmgr_sec_cm 36549886291181402531402967470010155170671746251563999577629286821899339966076 None
rstmgr_alert_test 66161739066388881790223677725282930294984764452855777861732840765622977403644 None