| V1 |
|
45.16% |
| V2 |
|
28.57% |
| V2S |
|
16.67% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 0.990s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_rw | 0.800s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 21.780s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_aliasing | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 13.857s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 5.470s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_rw | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_csr_rw | 13.956s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 105.280s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 41.910s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_busy | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_busy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_cmderr_not_supported | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_not_supported | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmderr_exception | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_exception | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_tl_access_resuming | 0 | 1 | 0.00 | |||
| rv_dm_mem_tl_access_resuming | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_tl_access_halted | 0 | 1 | 0.00 | |||
| rv_dm_mem_tl_access_halted | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmderr_halt_resume | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_halt_resume | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| dataaddr_rw_access | 0 | 1 | 0.00 | |||
| rv_dm_dataaddr_rw_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| halt_resume | 0 | 1 | 0.00 | |||
| rv_dm_halt_resume_whereto | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| progbuf_busy | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_busy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| abstractcmd_status | 0 | 1 | 0.00 | |||
| rv_dm_abstractcmd_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| progbuf_read_write_execute | 0 | 1 | 0.00 | |||
| rv_dm_progbuf_read_write_execute | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| progbuf_exception | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_exception | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_read_access | 0 | 1 | 0.00 | |||
| rv_dm_rom_read_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_hw_reset | 13.875s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.210s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_csr_bit_bash | 17.700s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_csr_aliasing | 19.090s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 2.360s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_dm_csr_aliasing | 19.090s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.210s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rv_dm_mem_walk | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rv_dm_mem_partial_access | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_hard_reset | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_hard_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_idle_hint | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_idle_hint | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_failed_op | 0 | 1 | 0.00 | |||
| rv_dm_dmi_failed_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_dm_inactive | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sba | 0 | 2 | 0.00 | |||
| rv_dm_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| bad_sba | 0 | 1 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sba_autoincrement | 0 | 1 | 0.00 | |||
| rv_dm_autoincr_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_debug_disabled | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sba_debug_disabled | 0 | 1 | 0.00 | |||
| rv_dm_sba_debug_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ndmreset_req | 0 | 1 | 0.00 | |||
| rv_dm_ndmreset_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hart_unavail | 0 | 1 | 0.00 | |||
| rv_dm_hart_unavail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tap_ctrl_transitions | 0 | 2 | 0.00 | |||
| rv_dm_tap_fsm_rand_reset | 17.940s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hartsel_warl | 0 | 1 | 0.00 | |||
| rv_dm_hartsel_warl | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rv_dm_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rv_dm_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_dm_tl_errors | 3.310s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_dm_tl_errors | 3.310s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| rv_dm_csr_aliasing | 19.090s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 13.875s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_rw | 1.210s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 2.850s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| rv_dm_csr_aliasing | 19.090s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 13.875s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_rw | 1.210s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 2.850s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| rv_dm_tl_intg_err | 19.600s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_dm_tl_intg_err | 19.600s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 2 | 0.00 | |||
| rv_dm_sba_debug_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_debug_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 0 | 2 | 0.00 | |||
| rv_dm_sba_debug_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_debug_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 0 | 1 | 0.00 | |||
| rv_dm_buffered_enable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_exec_ctrl_mubi | 0 | 1 | 0.00 | |||
| rv_dm_buffered_enable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rv_dm_scanmode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module tb
All of 103 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 17.315 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| rv_dm_jtag_dtm_csr_aliasing | 114259691673342727140519368132131001674020506331269160646276818312318375484039 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_jtag_dmi_csr_rw | 4161755013241103680380842927240329347764362336547716078123195541993545472611 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_tap_fsm_rand_reset | 64525777279189642373476919870582195276771594185263998999110665460264228405803 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_csr_hw_reset | 27789802070420898227827869489866236676641037463589701799772812522716149272951 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:43 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| rv_dm_smoke | 71646095594638380906472176913166347548718863869372067090688593005621247453205 | None | ||
| rv_dm_tap_fsm | 94773212159420648771973282853935909134152443647594073489662603888850781881738 | None | ||
| rv_dm_sba_tl_access | 24616558063117054843654390788241482850971548874483257503934858084728543456653 | None | ||
| rv_dm_delayed_resp_sba_tl_access | 57796596157726810154304646348311656219854643985323055573377880790369627733194 | None | ||
| rv_dm_bad_sba_tl_access | 92921032947194926728674869480252991717948864109286769095156089538302763797704 | None | ||
| rv_dm_autoincr_sba_tl_access | 60330972290243389699910697597469024068966289411687439333459703710153031555232 | None | ||
| rv_dm_cmderr_busy | 979591294052177596287374796485749313769455893603360292460332625651520424760 | None | ||
| rv_dm_cmderr_not_supported | 63415359833684153399477100282738785420733316607911714766740343735808233999720 | None | ||
| rv_dm_cmderr_exception | 51244748415701985327726108640463354876202297862395805419748194403589650963800 | None | ||
| rv_dm_mem_tl_access_halted | 39444831629462319353242803294195103447598936314111616428090694330494061624316 | None | ||
| rv_dm_mem_tl_access_resuming | 18274464783469378682192052141020180214119352584109313786734683645266142383511 | None | ||
| rv_dm_hart_unavail | 60557493728339930656541889088572600925459412308639197492105811088678501208405 | None | ||
| rv_dm_cmderr_halt_resume | 86816837126286025680756045036119040605947806790256295924958085279032574103889 | None | ||
| rv_dm_dataaddr_rw_access | 9277996328988866401774939507337379442688588797853871002028939005803406503695 | None | ||
| rv_dm_halt_resume_whereto | 2366500556926171574025903675772637583856884774771158913128029548369515961185 | None | ||
| rv_dm_sba_debug_disabled | 50063314114797219308861437727034147588431995005233036198043747759151111312813 | None | ||
| rv_dm_ndmreset_req | 109553786760251602491094652632979789472302369731404921915584329712098863479688 | None | ||
| rv_dm_jtag_dtm_idle_hint | 110128175771143078973302172885138610816146040926441722310780938760476536057161 | None | ||
| rv_dm_jtag_dmi_dm_inactive | 77366591120328926542826552718186746764889646369076901569632316394453951979750 | None | ||
| rv_dm_jtag_dmi_debug_disabled | 17941656269982324258428403109177143819970328321867049946796339232928040619116 | None | ||
| rv_dm_jtag_dtm_hard_reset | 68453869614560352445421542114089619578321659668264600009843958958491037013511 | None | ||
| rv_dm_abstractcmd_status | 33967563260160977654036701705268380233133282240272577564142650577513731345338 | None | ||
| rv_dm_rom_read_access | 36672211280074221305889298400794715562458583412257333811717079655002783688360 | None | ||
| rv_dm_progbuf_read_write_execute | 8614671587342710594298302733971270769608464082739130076035398296069626275706 | None | ||
| rv_dm_debug_disabled | 60337016828167709109214535615275819499922219306411960568111494342179356428544 | None | ||
| rv_dm_dmi_failed_op | 109087040134262373424007399723945837166778881689246794638211623550939715835867 | None | ||
| rv_dm_hartsel_warl | 111135378375549605657758725635226673818004363645090477600665142468187134606497 | None | ||
| rv_dm_buffered_enable | 99443324320833420618600628208159244161313395713974540091789150109079779119429 | None | ||
| rv_dm_sparse_lc_gate_fsm | 85937142711271841637893850324753779939766520180939292160523213658079533596364 | None | ||
| rv_dm_scanmode | 70695851133035092154010425869053488124852988141422092930282479585613026857266 | None | ||
| rv_dm_stress_all | 39191723318743697780290137219080414791068627208803302003169968107284509221580 | None | ||
| rv_dm_stress_all_with_rand_reset | 109035139592695170356076928661096164883059361369355550227517432462564869746167 | None | ||
| rv_dm_sec_cm | 69355770804592367546960625995983103716532750075586441729046084643072020056762 | None | ||
| rv_dm_alert_test | 66235802903626613368317911330710888137745412965531661436210308205852854919620 | None | ||