| V1 |
|
50.00% |
| V2 |
|
52.94% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 0 | 1 | 0.00 | |||
| rv_timer_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.550s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.540s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.110s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rv_timer_csr_aliasing | 36.308s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 42.552s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| rv_timer_csr_rw | 0.540s | 0.000us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 36.308s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disabled | 0 | 1 | 0.00 | |||
| rv_timer_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cfg_update_on_fly | 0 | 1 | 0.00 | |||
| rv_timer_cfg_update_on_fly | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| no_interrupt_test | 0 | 1 | 0.00 | |||
| rv_timer_cfg_update_on_fly | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress | 0 | 1 | 0.00 | |||
| rv_timer_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rv_timer_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.550s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.620s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.620s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| rv_timer_csr_hw_reset | 0.550s | 0.000us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.540s | 0.000us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 36.308s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_same_csr_outstanding | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| rv_timer_csr_hw_reset | 0.550s | 0.000us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.540s | 0.000us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 36.308s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_same_csr_outstanding | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| rv_timer_tl_intg_err | 13.845s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rv_timer_tl_intg_err | 13.845s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 1 | 0.00 | |||
| rv_timer_min | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | ||||
| default | None | None |
Job timed out after 60 minutes
|
|
| Job returned non-zero exit code | ||||
| rv_timer_tl_intg_err | 99861278727512845153272324024640096382137305438445194896607877124677179308957 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:42 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_timer_csr_aliasing | 16448417831544654532198601947749952724683523945104899877205540345584892046393 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:42 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_timer_csr_mem_rw_with_rand_reset | 113294413769831686347837224472324602405445089865367417434796898622280653120052 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:42 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_timer | None | None |
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-elfile needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| rv_timer_random | 45628302078361771224515005818334088906736102637511986582457554471523865807996 | None | ||
| rv_timer_min | 105891988085435379652227677664560614700167158130566774535396201321691833688190 | None | ||
| rv_timer_max | 36997927424071045788465607731264779853767297693670520412055163798189506409194 | None | ||
| rv_timer_disabled | 84192267022253538629978484387354717477129464640684039953834903801458095030539 | None | ||
| rv_timer_cfg_update_on_fly | 104988571738947734621907295027564586012776785965766650205698770699389146343081 | None | ||
| rv_timer_random_reset | 109948643308914177662558141555008877626069174825752089447742162871798827294916 | None | ||
| rv_timer_stress_all_with_rand_reset | 93200797358733312741260517934041866623818120451927896525619130515075789565641 | None | ||
| rv_timer_stress_all | 103884852904694501827347894784294154115779193049446893112201005479504650581932 | None | ||
| rv_timer_sec_cm | 51654111259416751292014855705519081866505869323832749049347569398944015663208 | None | ||
| rv_timer_alert_test | 22200925580921244787634159023822950254087417838765666651374955471892823617355 | None | ||