| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| spi_device_flash_and_tpm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| spi_device_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| spi_device_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| spi_device_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| spi_device_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 0 | 1 | 0.00 | |||
| spi_device_csb_read | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tpm_read | 0 | 1 | 0.00 | |||
| spi_device_tpm_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tpm_write | 0 | 1 | 0.00 | |||
| spi_device_tpm_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tpm_hw_reg | 0 | 2 | 0.00 | |||
| spi_device_tpm_read_hw_reg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_tpm_sts_read | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tpm_fully_random_case | 0 | 1 | 0.00 | |||
| spi_device_tpm_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pass_cmd_filtering | 0 | 2 | 0.00 | |||
| spi_device_pass_cmd_filtering | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pass_addr_translation | 0 | 2 | 0.00 | |||
| spi_device_pass_addr_payload_swap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pass_payload_translation | 0 | 2 | 0.00 | |||
| spi_device_pass_addr_payload_swap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_info_slots | 0 | 1 | 0.00 | |||
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_read_status | 0 | 2 | 0.00 | |||
| spi_device_intercept | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_read_jedec | 0 | 2 | 0.00 | |||
| spi_device_intercept | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_read_sfdp | 0 | 2 | 0.00 | |||
| spi_device_intercept | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_fast_read | 0 | 2 | 0.00 | |||
| spi_device_intercept | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_read_pipeline | 0 | 2 | 0.00 | |||
| spi_device_intercept | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| flash_cmd_upload | 0 | 1 | 0.00 | |||
| spi_device_upload | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mailbox_command | 0 | 1 | 0.00 | |||
| spi_device_mailbox | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mailbox_cross_outside_command | 0 | 1 | 0.00 | |||
| spi_device_mailbox | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mailbox_cross_inside_command | 0 | 1 | 0.00 | |||
| spi_device_mailbox | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_read_buffer | 0 | 2 | 0.00 | |||
| spi_device_flash_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_read_buffer_direct | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cmd_dummy_cycle | 0 | 2 | 0.00 | |||
| spi_device_mailbox | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| quad_spi | 0 | 1 | 0.00 | |||
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| dual_spi | 0 | 1 | 0.00 | |||
| spi_device_flash_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| 4b_3b_feature | 0 | 1 | 0.00 | |||
| spi_device_cfg_cmd | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| write_enable_disable | 0 | 1 | 0.00 | |||
| spi_device_cfg_cmd | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| TPM_with_flash_or_passthrough_mode | 0 | 1 | 0.00 | |||
| spi_device_flash_and_tpm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 0 | 1 | 0.00 | |||
| spi_device_flash_and_tpm_min_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| spi_device_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| spi_device_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| spi_device_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| spi_device_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| spi_device_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| spi_device_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| spi_device_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| spi_device_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| spi_device_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| spi_device_flash_mode_ignore_cmds | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | ||||
| default | None | None |
Job timed out after 60 minutes
|
|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 108 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 22.371 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| spi_device_tl_errors | 42044483309304872132527453528380311214122062762834126029435838658498294336855 | None | ||
| spi_device_tl_intg_err | 9633495480848639701647670562341199086858144508928678462254384198206317408011 | None | ||
| spi_device_intr_test | 31568878195636435395857031798993176201513866298552423175426606797910773617672 | None | ||
| spi_device_mem_walk | 17603444735522771656876260604512483298458024048788576525001687385958707707981 | None | ||
| spi_device_mem_partial_access | 21189275881869427754762358773134285609547843490505160602515343725447120914395 | None | ||
| spi_device_csr_hw_reset | 86557564902557062438703845700693649026858453306933328636899673698574288598965 | None | ||
| spi_device_csr_rw | 67036465443771748722143241765773165553164274272525858826126280773357590800667 | None | ||
| spi_device_csr_bit_bash | 54468524339574847146989621405525192439945093935939973265701746259343924614469 | None | ||
| spi_device_csr_aliasing | 80488737786904318798303115004847975698107111412092480159792442533304434882483 | None | ||
| spi_device_same_csr_outstanding | 111807566022858347498989581846296321706346779286681257201476171998525877423007 | None | ||
| spi_device_csr_mem_rw_with_rand_reset | 36485505498120545765110564764029927225367005961559545260521661619596593947173 | None | ||
| spi_device_csb_read | 115096210988296299064068277329174437997360545888457606978715311626902936283040 | None | ||
| spi_device_mem_parity | 105498097362916422169084173422512779920253380853438855391714498783055274741916 | None | ||
| spi_device_ram_cfg | 80205740220255138634020790686309055746148245704494026356351138543898434796169 | None | ||
| spi_device_tpm_read_hw_reg | 10505642908989436217928711439977028578001506559290361974505468978250626420235 | None | ||
| spi_device_tpm_all | 68831003013974359848989799761951352360010796947953349623964377063696043154170 | None | ||
| spi_device_tpm_sts_read | 115190875829793732027741351121675182148176972193650796709151162075644531036856 | None | ||
| spi_device_tpm_rw | 46081486079673573457009128065430358179465649052727604447662450108227592179472 | None | ||
| spi_device_pass_cmd_filtering | 633744341016489083386854884157964800701415554987977273100876593662710757603 | None | ||
| spi_device_pass_addr_payload_swap | 29738004518480063713018847420830716829629630464656703560367399463003206608350 | None | ||
| spi_device_intercept | 107164297033849459331233237336852340034335451789384556088434534535410035556963 | None | ||
| spi_device_mailbox | 67011344178287438493340514292196777377226729705405496795836850599160193118590 | None | ||
| spi_device_upload | 35140654217283704497165813058132041804332451207224114931668048848565206454588 | None | ||
| spi_device_cfg_cmd | 48191778304789899468646653892577930936361311358362715675225187824096491578689 | None | ||
| spi_device_flash_mode | 83291198884541901305416681322454028135603297661521395265204554352804424138997 | None | ||
| spi_device_flash_mode_ignore_cmds | 113504416008504565639221416834836303099788125567493138296595054247947015465362 | None | ||
| spi_device_read_buffer_direct | 34462757719905104784054981805590069894863911550721152726436704810408803115858 | None | ||
| spi_device_flash_all | 60239912333763535711589165755169528215290151050137331139010389852952547770189 | None | ||
| spi_device_flash_and_tpm | 4256138451886024011218740055934631178512349997611643568835617064791641477129 | None | ||
| spi_device_flash_and_tpm_min_idle | 23398533528114567259344266848554722740855357814590703548220166353068704617990 | None | ||
| spi_device_stress_all | 99973983479861395219389838797608115707189586122542721358998273719562988118722 | None | ||
| spi_device_sec_cm | 61316621570080251398278922868811267950674571472845279274896989020148995553492 | None | ||
| spi_device_alert_test | 39923693884947101024600105991197037551237942506328721737693361730742795621702 | None | ||
| spi_device | None | None | ||
| spi_device | None | None | ||