Simulation Results: sram_ctrl/main

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
30.00%
V2
60.00%
V2S
45.83%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 14.050s 0.000us 1 1 100.00
csr_hw_reset 0 1 0.00
sram_ctrl_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
sram_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
sram_ctrl_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
sram_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
sram_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
sram_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 83.960s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 94.450s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 154.660s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 141.140s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 741.350s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 275.070s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 48.200s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 228.740s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 11.690s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 170.310s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 15.810s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 10.570s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 39.420s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 280.070s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.100s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 888.050s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.610s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
sram_ctrl_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
sram_ctrl_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
sram_ctrl_csr_hw_reset 0.000s 0.000us 0 1 0.00
sram_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
sram_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
sram_ctrl_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
sram_ctrl_csr_hw_reset 0.000s 0.000us 0 1 0.00
sram_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
sram_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
sram_ctrl_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 0 1 0.00
sram_ctrl_passthru_mem_tl_intg_err 0.000s 0.000us 0 1 0.00
tl_intg_err 0 2 0.00
sram_ctrl_sec_cm 0.590s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 0.000s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.590s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
sram_ctrl_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 280.070s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 280.070s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 0 1 0.00
sram_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 228.740s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 228.740s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 228.740s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 48.200s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 13.871s 0.000us 0 1 0.00
sec_cm_mem_integrity 0 1 0.00
sram_ctrl_passthru_mem_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 41.910s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 14.050s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 14.050s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 228.740s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.590s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 48.200s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.590s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.590s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 14.050s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.590s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 40.185s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
cover_reg_top None None
Job timed out after 60 minutes
Job returned non-zero exit code
sram_ctrl_readback_err 66547061858083056412040974819289861559203402970588449878584295115215422376054 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:37 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_mubi_enc_err 35601235682405947398313890347540061097838802324674120078794489038970621999896 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:37 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_stress_all_with_rand_reset 115745321807015887368880953859656120275213813510514410409112735688955016794105 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:37 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 82963037090024392901737794649205451183751095427570082386030193259401769642019 99
UVM_ERROR @ 5476564 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5476564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed.
sram_ctrl_passthru_mem_tl_intg_err 74948696566310018300852041526452022655290237327308306871442319933431949462896 None
sram_ctrl_tl_errors 67685826601603137163604702738665582220135229894917933397121151048282661892258 None
sram_ctrl_tl_intg_err 12530143518763423903629069595422986035931403666466377861344143495962906313665 None
sram_ctrl_csr_hw_reset 24724525436776766630407981209009269032345818106296336962310514907194243255195 None
sram_ctrl_csr_rw 54776773366787661281675963219921291343942861103076539936080710114124775041951 None
sram_ctrl_csr_bit_bash 53458989731736386796916986036678991874615582612145331980544087028411931528022 None
sram_ctrl_csr_aliasing 56565430374657485914029013916024346947826457043328112763652236517301774603876 None
sram_ctrl_same_csr_outstanding 96708184488571059045292396278010042225269052813459876400528811885660507300943 None
sram_ctrl_csr_mem_rw_with_rand_reset 107776450050830196910789146556138936361737746767768274886598447609766374235460 None
sram_ctrl None None