| V1 |
|
50.00% |
| V2 |
|
32.00% |
| V2S |
|
12.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| sram_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| sram_ctrl_csr_hw_reset | 40.421s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 64.378s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sram_ctrl_csr_rw | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| sram_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| sram_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 0 | 1 | 0.00 | |||
| sram_ctrl_multiple_keys | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_pipeline | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_pipeline | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| bijection | 0 | 1 | 0.00 | |||
| sram_ctrl_bijection | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| access_during_key_req | 0 | 1 | 0.00 | |||
| sram_ctrl_access_during_key_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_escalation | 0 | 1 | 0.00 | |||
| sram_ctrl_lc_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| executable | 0 | 1 | 0.00 | |||
| sram_ctrl_executable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partial_access | 0 | 2 | 0.00 | |||
| sram_ctrl_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_partial_access_b2b | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| max_throughput | 0 | 3 | 0.00 | |||
| sram_ctrl_max_throughput | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_throughput_w_partial_write | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_throughput_w_readback | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen | 0 | 1 | 0.00 | |||
| sram_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ram_cfg | 0 | 1 | 0.00 | |||
| sram_ctrl_ram_cfg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| sram_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| sram_ctrl_csr_hw_reset | 40.421s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_csr_rw | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| sram_ctrl_csr_hw_reset | 40.421s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_csr_rw | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 30.275s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| sram_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_tl_intg_err | 1.130s | 0.000us | 1 | 1 | 100.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_intg_err | 1.130s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| sram_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_readback_config_regwen | 0 | 1 | 0.00 | |||
| sram_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_exec_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_mubi | 0 | 1 | 0.00 | |||
| sram_ctrl_executable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_exec_intersig_mubi | 0 | 1 | 0.00 | |||
| sram_ctrl_executable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 1 | 0.00 | |||
| sram_ctrl_executable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 0 | 1 | 0.00 | |||
| sram_ctrl_lc_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 1 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_integrity | 0 | 1 | 0.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 30.275s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_readback | 0 | 1 | 0.00 | |||
| sram_ctrl_readback_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 0 | 1 | 0.00 | |||
| sram_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_addr_scramble | 0 | 1 | 0.00 | |||
| sram_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_instr_bus_lc_gated | 0 | 1 | 0.00 | |||
| sram_ctrl_executable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_global_esc | 0 | 1 | 0.00 | |||
| sram_ctrl_lc_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_local_esc | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_init_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 0 | 1 | 0.00 | |||
| sram_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module sram_ctrl_cov_bind
All of 106 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 15.757 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| sram_ctrl_passthru_mem_tl_intg_err | 76679080342224616271943879672621935910082086212501991093286798413834449236505 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:46 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_csr_hw_reset | 21116336636933436865748927895889687840779842496299723763915155065404993428155 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:46 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_csr_mem_rw_with_rand_reset | 56334087285842041407582733623081531633933481456183959086265028493793633948950 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:46 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| Job killed most likely because its dependent job failed. | ||||
| sram_ctrl_smoke | 23951806443335857544071355742358087944722784344573617555093681275101563544348 | None | ||
| sram_ctrl_multiple_keys | 28935421848701425738473220892881184371155215082279757219156212087013759189601 | None | ||
| sram_ctrl_bijection | 41802247543568504019102845823755390422504017440050098222797173853738029701878 | None | ||
| sram_ctrl_stress_pipeline | 61097648074428246483140972956075271337586930544571112126010299858141824496148 | None | ||
| sram_ctrl_partial_access | 2586612390682540537342270620550941748188458255302172851827414645374215062927 | None | ||
| sram_ctrl_partial_access_b2b | 11404844372356676605532769361336985143447912493387716848331233176720963474679 | None | ||
| sram_ctrl_max_throughput | 23717106858822722624186947286042987095708469522835469868629695042917865837528 | None | ||
| sram_ctrl_throughput_w_partial_write | 77087445711036101990469943457313299548964513928297277792720508696073529120402 | None | ||
| sram_ctrl_throughput_w_readback | 92874952768032838042518850875898400860460635878038220571240546963876895718003 | None | ||
| sram_ctrl_lc_escalation | 13412563542488382971507310520170259383413115786628770769419354832969693349626 | None | ||
| sram_ctrl_access_during_key_req | 37816176686792084855479532344768211204383607878756852570499535143971337146562 | None | ||
| sram_ctrl_executable | 60144649369248704863743825678202814004996118662365540502217327941425921702935 | None | ||
| sram_ctrl_regwen | 67229353932508682245553371862959563506863699284748300029538488096961653495489 | None | ||
| sram_ctrl_ram_cfg | 27307564278927050254039204558369768824290136343550745607547083259597153314499 | None | ||
| sram_ctrl_mem_walk | 12095457252742898089274698674221731273892494037321632465422543636038664886260 | None | ||
| sram_ctrl_mem_partial_access | 68371753279352239659442389644270547415278503905431673173803411657067808523220 | None | ||
| sram_ctrl_readback_err | 107115885469597135755292567037361214262896860546425641928383387601482538850826 | None | ||
| sram_ctrl_mubi_enc_err | 114002125881452403621055029811227520045841031267071606034050986958287782625136 | None | ||
| sram_ctrl_stress_all_with_rand_reset | 47318568330462787698142553677356598741205938235729091408464226411583397865479 | None | ||
| sram_ctrl_stress_all | 41374083829510412836827683109427648428799004379751698437173423560052321623248 | None | ||
| sram_ctrl_sec_cm | 52018413805089995362674810706309450594690546917604848236671244235193898247564 | None | ||
| sram_ctrl_alert_test | 5477734331642369597377331278695492740433459674707287095145199964629269004548 | None | ||