Simulation Results: uart

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 57.81 %
  • code
  • 69.65 %
  • assert
  • 96.74 %
  • func
  • 7.05 %
  • line
  • 64.86 %
  • branch
  • 63.87 %
  • cond
  • 61.73 %
  • toggle
  • 88.13 %
Validation stages
V1
75.00%
V2
32.35%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
uart_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.570s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.760s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.650s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
uart_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.570s 0.000us 1 1 100.00
uart_csr_aliasing 0.650s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 0 1 0.00
uart_tx_rx 0.000s 0.000us 0 1 0.00
parity 0 2 0.00
uart_smoke 0.000s 0.000us 0 1 0.00
uart_tx_rx 0.000s 0.000us 0 1 0.00
parity_error 0 2 0.00
uart_intr 0.000s 0.000us 0 1 0.00
uart_rx_parity_err 0.000s 0.000us 0 1 0.00
watermark 0 2 0.00
uart_tx_rx 0.000s 0.000us 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
fifo_full 0 1 0.00
uart_fifo_full 0.000s 0.000us 0 1 0.00
fifo_overflow 0 1 0.00
uart_fifo_overflow 0.000s 0.000us 0 1 0.00
fifo_reset 0 1 0.00
uart_fifo_reset 0.000s 0.000us 0 1 0.00
rx_frame_err 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
rx_break_err 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
rx_timeout 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
perf 0 1 0.00
uart_perf 0.000s 0.000us 0 1 0.00
sys_loopback 0 1 0.00
uart_loopback 0.000s 0.000us 0 1 0.00
line_loopback 0 1 0.00
uart_loopback 0.000s 0.000us 0 1 0.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.000s 0.000us 0 1 0.00
rx_start_bit_filter 0 1 0.00
uart_rx_start_bit_filter 0.000s 0.000us 0 1 0.00
tx_overide 0 1 0.00
uart_tx_ovrd 0.000s 0.000us 0 1 0.00
rx_oversample 0 1 0.00
uart_rx_oversample 0.000s 0.000us 0 1 0.00
long_b2b_transfer 0 1 0.00
uart_long_xfer_wo_dly 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
uart_stress_all 0.000s 0.000us 0 1 0.00
alert_test 0 1 0.00
uart_alert_test 0.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
uart_intr_test 0.530s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.610s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.610s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 0.000us 1 1 100.00
uart_csr_rw 0.570s 0.000us 1 1 100.00
uart_csr_aliasing 0.650s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.660s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 0.000us 1 1 100.00
uart_csr_rw 0.570s 0.000us 1 1 100.00
uart_csr_aliasing 0.650s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.660s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
uart_tl_intg_err 1.080s 0.000us 1 1 100.00
uart_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
default None None
recompiling module tb
All of 75 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 13.976 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Job timed out after * minutes
uart_csr_mem_rw_with_rand_reset 90751774942495316687903622835614169841028019192757107362996103238257048236902 None
Job timed out after 60 minutes
Job killed most likely because its dependent job failed.
uart_smoke 49366789925621131237439257213589195883759659861103286534402704325094727101342 None
uart_tx_rx 8730736615084468967250036661936357273445829075621756013972415294894588654833 None
uart_fifo_full 47230555896043878618373000268842701807461873062554516319030845601541227203876 None
uart_fifo_overflow 6882769297518914750186104111958554893964642053114531016028058793570604174939 None
uart_fifo_reset 66934029901215882069417918832768282194369217781267137267146759233363632290323 None
uart_rx_oversample 2574180018668781301969937734201721893873354381250057856263565426146335691566 None
uart_intr 50582615020109735191773750193661092379930944111494203304009152908977804223941 None
uart_noise_filter 88506525286604331922455650609930298350620114963477388471766009856500443590135 None
uart_rx_start_bit_filter 97809184879905083930249429057103158072656524571933625089720744505911964578471 None
uart_rx_parity_err 86618390634682106934876158677704996055334109766503057773919650208797972764608 None
uart_tx_ovrd 64109151958583680091699991112107204612363845907000489307296434886400138212623 None
uart_loopback 17018720360226680073376794728181837777980457315507688550037430778392457390460 None
uart_perf 15057298084015736317703449610266155297354635052609318714628825265774184937781 None
uart_long_xfer_wo_dly 75191648152676802778612155490535086672273552717624655351028686947934954946134 None
uart_stress_all_with_rand_reset 67475488721920072471611675908680880359913352260017224773704605909340752236409 None
uart_stress_all 5180267250931622342602345258547899480061073417209631627866502388142515529506 None
uart_sec_cm 72102251367137155055378447676097997543687840263028554181683162812576104437875 None
uart_alert_test 26013801114198119169729924144388948170038886147887814109350888915837528425621 None