| V1 |
|
12.50% |
| V2 |
|
41.67% |
| V2S |
|
33.33% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 48.700s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| alert_handler_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| alert_handler_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| alert_handler_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| alert_handler_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| alert_handler_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 1 | 1 | 100.00 | |||
| alert_handler_esc_alert_accum | 79.710s | 0.000us | 1 | 1 | 100.00 | |
| esc_timeout | 0 | 1 | 0.00 | |||
| alert_handler_esc_intr_timeout | 18.104s | 0.000us | 0 | 1 | 0.00 | |
| entropy | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 907.930s | 0.000us | 1 | 1 | 100.00 | |
| sig_int_fail | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 4.230s | 0.000us | 1 | 1 | 100.00 | |
| clk_skew | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 48.700s | 0.000us | 1 | 1 | 100.00 | |
| random_alerts | 1 | 1 | 100.00 | |||
| alert_handler_random_alerts | 30.140s | 0.000us | 1 | 1 | 100.00 | |
| random_classes | 1 | 1 | 100.00 | |||
| alert_handler_random_classes | 8.600s | 0.000us | 1 | 1 | 100.00 | |
| ping_timeout | 0 | 1 | 0.00 | |||
| alert_handler_ping_timeout | 28.800s | 0.000us | 0 | 1 | 0.00 | |
| lpg | 2 | 2 | 100.00 | |||
| alert_handler_lpg | 1119.750s | 0.000us | 1 | 1 | 100.00 | |
| alert_handler_lpg_stub_clk | 1254.880s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| alert_handler_stress_all | 19.582s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_entropy_stress_test | 1 | 1 | 100.00 | |||
| alert_handler_entropy_stress | 33.510s | 0.000us | 1 | 1 | 100.00 | |
| alert_handler_alert_accum_saturation | 1 | 1 | 100.00 | |||
| alert_handler_alert_accum_saturation | 1.880s | 0.000us | 1 | 1 | 100.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| alert_handler_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| alert_handler_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| alert_handler_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| alert_handler_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| alert_handler_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| alert_handler_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_shadow | 0 | 1 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ping_timer_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 48.700s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_alert_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 48.700s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 48.700s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_class_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 48.700s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_alert_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 4.230s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 1 | 1 | 100.00 | |||
| alert_handler_lpg | 1119.750s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_esc_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 4.230s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 907.930s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 907.930s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ping_timer_fsm_sparse | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_timer_fsm_local_esc | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ping_timer_fsm_local_esc | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_timer_fsm_global_esc | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_accu_ctr_redun | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_timer_ctr_redun | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ping_timer_ctr_redun | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ping_timer_lfsr_redun | 0 | 1 | 0.00 | |||
| alert_handler_sec_cm | 11.946s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_stress_all_with_rand_reset | 147.570s | 0.000us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 100 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 26.599 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| alert_handler_esc_intr_timeout | 51229621800868856439093665481149875903574399672264829870782611174043096902770 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:20 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| alert_handler_stress_all | 109589939024488480080655213793903717802206128584022781139283525315477941020238 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:20 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| alert_handler_sec_cm | 99086758870942873660989504427294585010022572746391485346359017097319475271955 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:20 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| alert_handler | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | ||||
| alert_handler_ping_timeout | 113514324643030277240481252050620109427520080527571377500333325102965932710816 | 87 |
UVM_ERROR @ 19950911768 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 19950911768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job killed most likely because its dependent job failed. | ||||
| alert_handler_shadow_reg_errors_with_csr_rw | 86771481224769567942005881256183720372959498177532725190021235769393114770022 | None | ||
| alert_handler_shadow_reg_errors | 51500517591452536080816422212308471092696828953681784914357693810603848706057 | None | ||
| alert_handler_tl_errors | 35713016735932216675625983882652430999129082327525086228508963360739261346189 | None | ||
| alert_handler_tl_intg_err | 64032157229735241759630621813866994151392726661932640531967638486803219521416 | None | ||
| alert_handler_intr_test | 73455740834556074846008271356174586968909202964327356916927150008572613587527 | None | ||
| alert_handler_csr_hw_reset | 61714213968313689653122623070399269642804798162237775779827836462757043907913 | None | ||
| alert_handler_csr_rw | 3619353001761646787434376253984283614548374906643100680232274763560480614914 | None | ||
| alert_handler_csr_bit_bash | 20929530547169868834828046246319005615912151777851013072510551665793531346621 | None | ||
| alert_handler_csr_aliasing | 94014862130462162995268107572637892960098549944443928967741782314717210361931 | None | ||
| alert_handler_same_csr_outstanding | 113168213212885018254673029970183287608836668593180671527503406963510365738830 | None | ||
| alert_handler_csr_mem_rw_with_rand_reset | 16282666398794412150414765997868879439411539312020931965015159681531276082551 | None | ||