| V1 |
|
50.00% |
| V2 |
|
36.84% |
| V2S |
|
29.41% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 1.060s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 35.935s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 56.952s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| clkmgr_csr_aliasing | 0.760s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 1.080s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.760s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 1 | 1 | 100.00 | |||
| clkmgr_peri | 0.780s | 0.000us | 1 | 1 | 100.00 | |
| trans_enables | 1 | 1 | 100.00 | |||
| clkmgr_trans | 0.750s | 0.000us | 1 | 1 | 100.00 | |
| clk_status | 1 | 1 | 100.00 | |||
| clkmgr_clk_status | 0.800s | 0.000us | 1 | 1 | 100.00 | |
| jitter | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 1.060s | 0.000us | 1 | 1 | 100.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 36.255s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 13.861s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 36.255s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 66.339s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| clkmgr_alert_test | 0.920s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 34.174s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 34.174s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 1 | 4 | 25.00 | |||
| clkmgr_csr_hw_reset | 35.935s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.760s | 0.000us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 58.272s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 1 | 4 | 25.00 | |||
| clkmgr_csr_hw_reset | 35.935s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.760s | 0.000us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 58.272s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 34.302s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.740s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 3.510s | 0.000us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 3.510s | 0.000us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 3.510s | 0.000us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 3.510s | 0.000us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.740s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 36.255s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 13.861s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 3.510s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 38.266s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 34.302s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.580s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 34.302s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 15.979s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 1.910s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| clkmgr_frequency | 112047739289005203330541990568562730607992582399751564115294038116604948912440 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_frequency_timeout | 27346114492457941267538099027765628332968643888771961140138419961068365770414 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_idle_intersig_mubi | 5106750615258794913697052382750741643572158563963821449173209690867641728109 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_regwen | 93524867342057076240564655953067922797726702170192414631791985382993880967480 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_sec_cm | 89237677964599019260390881133371694234916377960198230419153425926383842345283 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_stress_all | 72718361979876814307797062777324808878774252712622364624455894460518748049300 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_tl_errors | 84097245414304026878448524029915751831013728747546890184007938120081436079547 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_csr_hw_reset | 111928280709471879407809666099436333894655340411749752178019654684308661390982 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_csr_bit_bash | 31957668827407255169340397312160894268044252800075355806027006285596136571257 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr_same_csr_outstanding | 29563988059732553413408324822802008132790979607829956338619856427029229784923 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| clkmgr | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* | ||||
| clkmgr_stress_all_with_rand_reset | 66536372693303918651474634719202989749981362917381250683324612841863663153827 | 102 |
UVM_ERROR @ 105676603 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 105676603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * | ||||
| clkmgr_shadow_reg_errors_with_csr_rw | 74650159680118480515360222328570460566289621665234368031038201874417568132823 | 75 |
UVM_ERROR @ 3904319 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 3904319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| clkmgr_tl_intg_err | 17467936529258355229748720887359840877787345812420474726062433399094133969999 | 100 |
UVM_ERROR @ 12683168 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 12683168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * | ||||
| clkmgr_csr_rw | 41578693493444568647327970989174197195613911245443966181089293671642041169734 | 75 |
UVM_ERROR @ 3792877 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 3792877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|