Simulation Results: edn/edn0

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
75.00%
V2
85.71%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 0.000us 1 1 100.00
csr_hw_reset 0 1 0.00
edn_csr_hw_reset 11.931s 0.000us 0 1 0.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 0.000us 1 1 100.00
csr_bit_bash 0 1 0.00
edn_csr_bit_bash 30.289s 0.000us 0 1 0.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 0.000us 1 1 100.00
edn_csr_aliasing 1.200s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.980s 0.000us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.980s 0.000us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.980s 0.000us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.740s 0.000us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 0.000us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 0.000us 1 1 100.00
disable 1 2 50.00
edn_disable 36.307s 0.000us 0 1 0.00
edn_disable_auto_req_mode 0.940s 0.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.260s 0.000us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 0.000us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.740s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.740s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
edn_csr_hw_reset 11.931s 0.000us 0 1 0.00
edn_csr_rw 0.790s 0.000us 1 1 100.00
edn_csr_aliasing 1.200s 0.000us 1 1 100.00
edn_same_csr_outstanding 1.040s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
edn_csr_hw_reset 11.931s 0.000us 0 1 0.00
edn_csr_rw 0.790s 0.000us 1 1 100.00
edn_csr_aliasing 1.200s 0.000us 1 1 100.00
edn_same_csr_outstanding 1.040s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.600s 0.000us 1 1 100.00
edn_tl_intg_err 1.220s 0.000us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.730s 0.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 0.000us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.600s 0.000us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.600s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.600s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.600s 0.000us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 0.000us 1 1 100.00
edn_sec_cm 6.600s 0.000us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 0.000us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.220s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 11.875s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
edn_stress_all_with_rand_reset 109736546161425744745163031501589001105260234535383076347375808135442723832991 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
edn_disable 20688534717312550533238686356270058571711440313185428335281811379503408655568 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
edn_csr_hw_reset 59704518511544258682139633974655251384561081108540231000058186096699930652356 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:21 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
edn_csr_bit_bash 25949609150847394192801208356959509470814497760990119999964146711748988702908 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:21 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
edn None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1