Simulation Results: edn/edn1

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 58.34 %
  • code
  • 32.37 %
  • assert
  • 95.81 %
  • func
  • 46.85 %
  • line
  • 39.76 %
  • branch
  • 42.86 %
  • cond
  • 30.85 %
  • toggle
  • 48.40 %
  • FSM
  • 0.00 %
Validation stages
V1
62.50%
V2
42.86%
V2S
16.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
edn_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 0 1 0.00
edn_csr_hw_reset 12.026s 0.000us 0 1 0.00
csr_rw 1 1 100.00
edn_csr_rw 0.700s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.030s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
edn_csr_mem_rw_with_rand_reset 9.900s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.700s 0.000us 1 1 100.00
edn_csr_aliasing 1.030s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 0 1 0.00
edn_genbits 0.000s 0.000us 0 1 0.00
csrng_commands 0 1 0.00
edn_genbits 0.000s 0.000us 0 1 0.00
genbits 0 1 0.00
edn_genbits 0.000s 0.000us 0 1 0.00
interrupts 0 1 0.00
edn_intr 0.000s 0.000us 0 1 0.00
alerts 0 1 0.00
edn_alert 0.000s 0.000us 0 1 0.00
errs 0 1 0.00
edn_err 0.000s 0.000us 0 1 0.00
disable 0 2 0.00
edn_disable 0.000s 0.000us 0 1 0.00
edn_disable_auto_req_mode 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
edn_stress_all 0.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
edn_intr_test 0.730s 0.000us 1 1 100.00
alert_test 0 1 0.00
edn_alert_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.010s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.010s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
edn_csr_hw_reset 12.026s 0.000us 0 1 0.00
edn_csr_rw 0.700s 0.000us 1 1 100.00
edn_csr_aliasing 1.030s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.920s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
edn_csr_hw_reset 12.026s 0.000us 0 1 0.00
edn_csr_rw 0.700s 0.000us 1 1 100.00
edn_csr_aliasing 1.030s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.920s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
edn_tl_intg_err 1.230s 0.000us 1 1 100.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_config_regwen 0 1 0.00
edn_regwen 0.000s 0.000us 0 1 0.00
sec_cm_config_mubi 0 1 0.00
edn_alert 0.000s 0.000us 0 1 0.00
sec_cm_main_sm_fsm_sparse 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_ack_sm_fsm_sparse 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_fifo_ctr_redun 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_main_sm_ctr_local_esc 0 2 0.00
edn_alert 0.000s 0.000us 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_cs_rdata_bus_consistency 0 1 0.00
edn_alert 0.000s 0.000us 0 1 0.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.230s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
default None None
recompiling module tb
All of 91 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 18.309 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
edn_csr_hw_reset 59369955833414897934903576441816644774414614262091162977780240740852613588048 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
edn_csr_mem_rw_with_rand_reset 78438975407326459999715765590775902185126553315010413688309882090287598200592 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
Job killed most likely because its dependent job failed.
edn_smoke 66078638022655071685990842662335772523379244307179580275701608569241259433547 None
edn_regwen 96029898201874661068389862439192374716972702973202458067507620728074217822828 None
edn_genbits 83171891444068962542818023558696007174312014858779447252970188939261274939498 None
edn_stress_all 80263841133745985867437208637058110798057034934583145990464578166783851353817 None
edn_stress_all_with_rand_reset 67586735541872494076709929527549888038810438286767820428612374373846309425726 None
edn_intr 69856256323909107956448250047528227993539227029430672179208958760404691205079 None
edn_alert 22415393581980812449525551094186518015777496688348690174601675305383406900936 None
edn_err 29171035632550281326005456463431788397980057766776124171110214249171243293802 None
edn_disable 83275857850179819309238533126975871044833849056662973511542262390442472957881 None
edn_disable_auto_req_mode 7190570159320215289429566101288007652950959500218910506768675433639318778107 None
edn_sec_cm 111293288682548775192921113612418399882639310217176769353968690186388604105781 None
edn_alert_test 65119517889847521208636293581776735823657591770041225211645607564773384428676 None