| V1 |
|
75.00% |
| V2 |
|
12.50% |
| V2S |
|
66.67% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| hmac_csr_hw_reset | 32.262s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| hmac_csr_rw | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| hmac_csr_bit_bash | 7.540s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| hmac_csr_aliasing | 2.450s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| hmac_csr_mem_rw_with_rand_reset | 531.330s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| hmac_csr_rw | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| hmac_csr_aliasing | 2.450s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg | 0 | 1 | 0.00 | |||
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| back_pressure | 0 | 1 | 0.00 | |||
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_vectors | 0 | 6 | 0.00 | |||
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| burst_wr | 0 | 1 | 0.00 | |||
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| datapath_stress | 0 | 1 | 0.00 | |||
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| hmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| wipe_secret | 0 | 1 | 0.00 | |||
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| save_and_restore | 0 | 6 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| fifo_empty_status_interrupt | 0 | 11 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| wide_digest_configurable_key_length | 0 | 14 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| hmac_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| hmac_intr_test | 0.550s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| hmac_tl_errors | 26.353s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| hmac_tl_errors | 26.353s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| hmac_csr_hw_reset | 32.262s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_rw | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| hmac_csr_aliasing | 2.450s | 0.000us | 1 | 1 | 100.00 | |
| hmac_same_csr_outstanding | 1.260s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| hmac_csr_hw_reset | 32.262s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_rw | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| hmac_csr_aliasing | 2.450s | 0.000us | 1 | 1 | 100.00 | |
| hmac_same_csr_outstanding | 1.260s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| hmac_tl_intg_err | 2.110s | 0.000us | 1 | 1 | 100.00 | |
| hmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| hmac_tl_intg_err | 2.110s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| write_config_and_secret_key_during_msg_wr | 0 | 1 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_reset | 0 | 1 | 0.00 | |||
| hmac_stress_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| hmac_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| hmac_directed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module tb
All of 81 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 14.099 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| hmac_tl_errors | 104132565002152408597988237644261874057669866066508371070372877309579441946373 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| hmac_csr_hw_reset | 86947093987192760972440979105099495177832662579490671608457558891263823503190 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| hmac | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| hmac_smoke | 110646838451210314895310717025572495167082916944427165096862009764536004993779 | None | ||
| hmac_long_msg | 50437942285636481432196531442475409957027690640616993732106985527523699321542 | None | ||
| hmac_stress_reset | 99157529350163427273176124430209698764236204883440266446124760407155011844898 | None | ||
| hmac_back_pressure | 64078038014623457336048810109101978602449995409306109570459325881842456588554 | None | ||
| hmac_datapath_stress | 55021110667817911533488313726549407437293596031617453231981999069199679426882 | None | ||
| hmac_burst_wr | 85073494110320850717357899299972507154668760220402149207218675796450210834960 | None | ||
| hmac_error | 26531941634786943568070677813972965263489275303847519708259508556479098932515 | None | ||
| hmac_wipe_secret | 23357154285811139919802698907494296117311160744518720400983030967444460363644 | None | ||
| hmac_test_sha256_vectors | 78732303175846296180246509158504465109309834960535264276567101798703737403330 | None | ||
| hmac_test_sha384_vectors | 11080415994112462572952952046080624232612579581403835004568851773950254200755 | None | ||
| hmac_test_sha512_vectors | 105637186796734780571535226131560128021167759561168862312035435251874019658056 | None | ||
| hmac_test_hmac256_vectors | 35681034536467477888762413036446498029317307161348409428531110217076464558143 | None | ||
| hmac_test_hmac384_vectors | 45619058606007150539629973302994202164455856114499249962346064392878087331740 | None | ||
| hmac_test_hmac512_vectors | 105572204955927274993392092151764302332215283559735238369669718985033490959796 | None | ||
| hmac_stress_all | 86052729340335632992539438832256183731792128567755220582827552933181089849606 | None | ||
| hmac_stress_all_with_rand_reset | 75306143553061035320733463291964111995751679201965707750431975823703422840267 | None | ||
| hmac_directed | 6997821088731487315692226071113945349415873852799884982404808831998967362364 | None | ||
| hmac_sec_cm | 13983441527154383092316575313878288670002256449432407468422813099062312913241 | None | ||
| hmac_alert_test | 21080603995248172629875638648703543070006181126030503388847985505648469636672 | None | ||