| V1 |
|
22.22% |
| V2 |
|
55.10% |
| V2S |
|
33.33% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_smoke | 1 | 1 | 100.00 | |||
| i2c_host_smoke | 12.090s | 0.000us | 1 | 1 | 100.00 | |
| target_smoke | 1 | 1 | 100.00 | |||
| i2c_target_smoke | 7.110s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| i2c_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| i2c_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_error_intr | 0 | 1 | 0.00 | |||
| i2c_host_error_intr | 0.620s | 0.000us | 0 | 1 | 0.00 | |
| host_stress_all | 0 | 1 | 0.00 | |||
| i2c_host_stress_all | 335.590s | 0.000us | 0 | 1 | 0.00 | |
| host_maxperf | 0 | 1 | 0.00 | |||
| i2c_host_perf | 38.288s | 0.000us | 0 | 1 | 0.00 | |
| host_override | 1 | 1 | 100.00 | |||
| i2c_host_override | 0.590s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_watermark | 1 | 1 | 100.00 | |||
| i2c_host_fifo_watermark | 90.860s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_overflow | 1 | 1 | 100.00 | |||
| i2c_host_fifo_overflow | 42.060s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_reset | 3 | 3 | 100.00 | |||
| i2c_host_fifo_reset_fmt | 0.810s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_fifo_fmt_empty | 5.670s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_fifo_reset_rx | 7.560s | 0.000us | 1 | 1 | 100.00 | |
| host_fifo_full | 1 | 1 | 100.00 | |||
| i2c_host_fifo_full | 61.980s | 0.000us | 1 | 1 | 100.00 | |
| host_timeout | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 10.110s | 0.000us | 1 | 1 | 100.00 | |
| i2c_host_mode_toggle | 1 | 1 | 100.00 | |||
| i2c_host_mode_toggle | 1.250s | 0.000us | 1 | 1 | 100.00 | |
| target_glitch | 0 | 1 | 0.00 | |||
| i2c_target_glitch | 1.960s | 0.000us | 0 | 1 | 0.00 | |
| target_stress_all | 1 | 1 | 100.00 | |||
| i2c_target_stress_all | 83.810s | 0.000us | 1 | 1 | 100.00 | |
| target_maxperf | 0 | 1 | 0.00 | |||
| i2c_target_perf | 13.826s | 0.000us | 0 | 1 | 0.00 | |
| target_fifo_empty | 2 | 2 | 100.00 | |||
| i2c_target_stress_rd | 5.680s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_intr_smoke | 4.370s | 0.000us | 1 | 1 | 100.00 | |
| target_fifo_reset | 2 | 2 | 100.00 | |||
| i2c_target_fifo_reset_acq | 1.240s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_fifo_reset_tx | 0.840s | 0.000us | 1 | 1 | 100.00 | |
| target_fifo_full | 3 | 3 | 100.00 | |||
| i2c_target_stress_wr | 29.840s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_stress_rd | 5.680s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_intr_stress_wr | 83.100s | 0.000us | 1 | 1 | 100.00 | |
| target_timeout | 1 | 1 | 100.00 | |||
| i2c_target_timeout | 3.970s | 0.000us | 1 | 1 | 100.00 | |
| target_clock_stretch | 0 | 1 | 0.00 | |||
| i2c_target_stretch | 13.942s | 0.000us | 0 | 1 | 0.00 | |
| bad_address | 1 | 1 | 100.00 | |||
| i2c_target_bad_addr | 3.180s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_glitch | 0 | 1 | 0.00 | |||
| i2c_target_hrst | 16.087s | 0.000us | 0 | 1 | 0.00 | |
| target_fifo_watermark | 2 | 2 | 100.00 | |||
| i2c_target_fifo_watermarks_acq | 1.660s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_fifo_watermarks_tx | 0.960s | 0.000us | 1 | 1 | 100.00 | |
| host_mode_config_perf | 1 | 2 | 50.00 | |||
| i2c_host_perf | 38.288s | 0.000us | 0 | 1 | 0.00 | |
| i2c_host_perf_precise | 1.840s | 0.000us | 1 | 1 | 100.00 | |
| host_mode_clock_stretching | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 10.110s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_tx_stretch_ctrl | 1 | 1 | 100.00 | |||
| i2c_target_tx_stretch_ctrl | 1.980s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_nack_generation | 1 | 3 | 33.33 | |||
| i2c_target_nack_acqfull | 1.920s | 0.000us | 1 | 1 | 100.00 | |
| i2c_target_nack_acqfull_addr | 17.635s | 0.000us | 0 | 1 | 0.00 | |
| i2c_target_nack_txstretch | 34.272s | 0.000us | 0 | 1 | 0.00 | |
| host_mode_halt_on_nak | 1 | 1 | 100.00 | |||
| i2c_host_may_nack | 3.470s | 0.000us | 1 | 1 | 100.00 | |
| target_mode_smbus_maxlen | 0 | 1 | 0.00 | |||
| i2c_target_smbus_maxlen | 34.206s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| i2c_alert_test | 0.580s | 0.000us | 1 | 1 | 100.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| i2c_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| i2c_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| i2c_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| i2c_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| i2c_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| i2c_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| i2c_sec_cm | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| i2c_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| i2c_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_host_stress_all_with_rand_reset | 5.170s | 0.000us | 0 | 1 | 0.00 | |
| target_error_intr | 0 | 1 | 0.00 | |||
| i2c_target_unexp_stop | 1.010s | 0.000us | 0 | 1 | 0.00 | |
| target_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_target_stress_all_with_rand_reset | 38.612s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 82 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 16.978 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| i2c_host_perf | 112495057890747606175930303097268235573701890137265935898164183417372392907064 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_stretch | 77465327295172970453673194085079798069794721259970321911054358674935540140248 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_perf | 48267216798741734052229401840403578221020611641105594506146361631850795226080 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_hrst | 110194270023836018583181711256345182905526880371900375019592379422878861369400 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_stress_all_with_rand_reset | 103140475270295600546026439788733489585062870099480242117170878099692039862831 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_smbus_maxlen | 95032368732667433596212155311888947891877915468234975752498817605990411176126 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_nack_acqfull_addr | 100314096435276727906083861006283522207172519613824213265408094809136353361551 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| i2c_target_nack_txstretch | 37072645170131164684940156675304646766708859123068556960909465930953527632334 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between | ||||
| i2c_host_error_intr | 78781113077968916713621890041831742278075138690771215218093169584052221644550 | 86 |
UVM_ERROR @ 32681874 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 32681874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_host_stress_all | 98741135146834291791701233753725435832983940650319347945545411079247421876529 | 155 |
UVM_ERROR @ 32279505510 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 32279505510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between | ||||
| i2c_target_glitch | 88597328516050097809111465784391178663828542883854655336796880305889077219895 | 84 |
UVM_ERROR @ 3203557761 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 3203557761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) | ||||
| i2c_target_unexp_stop | 35736183069078737390882418682125248676554582071348889311691168895035710433611 | 78 |
UVM_ERROR @ 198364375 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 120 [0x78])
UVM_INFO @ 198364375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| i2c_host_stress_all_with_rand_reset | 16608233270478255691721068949169919180755902692652154001405227571958824774189 | 92 |
UVM_ERROR @ 2299758953 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2299758953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job killed most likely because its dependent job failed. | ||||
| i2c_tl_errors | 1665834105395737089416538525436238080113402889686068883920568884058127645891 | None | ||
| i2c_tl_intg_err | 84721219347356145263638814492581391235802917270109818263719680738988305142617 | None | ||
| i2c_intr_test | 16090674896716347942483579285626872529555870407783494833029407247312908762861 | None | ||
| i2c_csr_hw_reset | 64432620432818070054741721116259462893715656479568815369304028411419274004261 | None | ||
| i2c_csr_rw | 56065084028198667193884382113549330364267667228086088388338282071698071033183 | None | ||
| i2c_csr_bit_bash | 21716609790557838074605109490461710306114431297466094058805737610524426661691 | None | ||
| i2c_csr_aliasing | 65765892507957614624716496943623559053179274526844442862359462329862378448590 | None | ||
| i2c_same_csr_outstanding | 1330572054942823704166942673037570129150056982457991688532008915623557254536 | None | ||
| i2c_csr_mem_rw_with_rand_reset | 64070454798132642152644276030879075753074311414713047688749141262111337962269 | None | ||