Simulation Results: keymgr

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
11.11%
V2
54.17%
V2S
60.53%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.930s 0.000us 1 1 100.00
random 0 1 0.00
keymgr_random 13.932s 0.000us 0 1 0.00
csr_hw_reset 0 1 0.00
keymgr_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
keymgr_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
keymgr_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
keymgr_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
keymgr_csr_aliasing 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 7.080s 0.000us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 1.650s 0.000us 1 1 100.00
keymgr_sideload_kmac 1.940s 0.000us 1 1 100.00
keymgr_sideload_aes 3.740s 0.000us 1 1 100.00
keymgr_sideload_otbn 2.790s 0.000us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.390s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.720s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.350s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.970s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.250s 0.000us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 4.440s 0.000us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 12.310s 0.000us 1 1 100.00
intr_test 0 1 0.00
keymgr_intr_test 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
keymgr_alert_test 0.670s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
keymgr_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
keymgr_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
keymgr_csr_hw_reset 0.000s 0.000us 0 1 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
keymgr_csr_aliasing 0.000s 0.000us 0 1 0.00
keymgr_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
keymgr_csr_hw_reset 0.000s 0.000us 0 1 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
keymgr_csr_aliasing 0.000s 0.000us 0 1 0.00
keymgr_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
keymgr_tl_intg_err 0.000s 0.000us 0 1 0.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_shadow_reg_errors_with_csr_rw 0.000s 0.000us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
keymgr_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_config_shadow 0 1 0.00
keymgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 7.080s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 0 2 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
keymgr_random 13.932s 0.000us 0 1 0.00
sec_cm_sw_binding_config_regwen 0 2 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
keymgr_random 13.932s 0.000us 0 1 0.00
sec_cm_max_key_ver_config_regwen 0 2 0.00
keymgr_csr_rw 0.000s 0.000us 0 1 0.00
keymgr_random 13.932s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.720s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.250s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.250s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 0 1 0.00
keymgr_random 13.932s 0.000us 0 1 0.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.140s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.320s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.720s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.320s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.320s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.320s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.570s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.320s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 5.450s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
cover_reg_top None None
recompiling module keymgr_cov_bind
All of 108 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 29.660 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
keymgr_random 70667654891616349686886648517315190270928770280175134634053115504068209319212 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:14 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
keymgr None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
Job killed most likely because its dependent job failed.
keymgr_shadow_reg_errors 67672360453934280712117487985701804654137613287314645476190756871543656186219 None
keymgr_shadow_reg_errors_with_csr_rw 53746156011881159252143280387613617872769135552995757177903848274935987334882 None
keymgr_tl_errors 55857259083417266532988425881445582057756986221497795824943245153051251301716 None
keymgr_tl_intg_err 112587246264428370879788132336170465678706571646857274014502978289967977221724 None
keymgr_intr_test 42427532475535276968856505683318347035238698364701077495826789517505772726135 None
keymgr_csr_hw_reset 81931736913011425846168092814546477192778329134374885793685447998456209612241 None
keymgr_csr_rw 36322069486855873851102558542579294648763003245389857625413223245498886434329 None
keymgr_csr_bit_bash 88797103061727840831831763745480692169226522973147955084046832133530249567354 None
keymgr_csr_aliasing 45192671244000190256276654095197039549897815354735703718042710482766445526170 None
keymgr_same_csr_outstanding 31220861900664898802368131244988391255397246765924235677357107462405771835172 None
keymgr_csr_mem_rw_with_rand_reset 78281028350672384437959745953995699803345906614949855697431563390061420724919 None
keymgr None None