| V1 |
|
75.00% |
| V2 |
|
70.00% |
| V2S |
|
96.43% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| lc_ctrl_smoke | 1.350s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.900s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_rw | 0.820s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_bit_bash | 0.880s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_aliasing | 17.645s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 1.090s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| lc_ctrl_csr_rw | 0.820s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 17.645s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 1 | 1 | 100.00 | |||
| lc_ctrl_state_post_trans | 2.340s | 0.000us | 1 | 1 | 100.00 | |
| regwen_during_op | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 5.120s | 0.000us | 1 | 1 | 100.00 | |
| rand_wr_claim_transition_if | 0 | 1 | 0.00 | |||
| lc_ctrl_claim_transition_if | 38.258s | 0.000us | 0 | 1 | 0.00 | |
| lc_prog_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_prog_failure | 38.243s | 0.000us | 0 | 1 | 0.00 | |
| lc_state_failure | 1 | 1 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_errors | 1 | 1 | 100.00 | |||
| lc_ctrl_errors | 7.430s | 0.000us | 1 | 1 | 100.00 | |
| security_escalation | 5 | 7 | 71.43 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_prog_failure | 38.243s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_errors | 7.430s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_security_escalation | 5.540s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_failure | 75.900s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_prog_failure | 13.969s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_errors | 33.520s | 0.000us | 1 | 1 | 100.00 | |
| jtag_access | 8 | 13 | 61.54 | |||
| lc_ctrl_jtag_csr_hw_reset | 34.377s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_rw | 1.520s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_bit_bash | 13.360s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_aliasing | 3.660s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 0.990s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 1.550s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_alert_test | 13.866s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_smoke | 3.350s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 6.980s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_prog_failure | 13.969s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_errors | 33.520s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_access | 32.435s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_regwen_during_op | 36.305s | 0.000us | 0 | 1 | 0.00 | |
| jtag_priority | 1 | 1 | 100.00 | |||
| lc_ctrl_jtag_priority | 5.340s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_volatile_unlock | 1 | 1 | 100.00 | |||
| lc_ctrl_volatile_unlock_smoke | 0.820s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| lc_ctrl_stress_all | 73.650s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| lc_ctrl_alert_test | 13.985s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.660s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.660s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| lc_ctrl_csr_hw_reset | 0.900s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.820s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 17.645s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_same_csr_outstanding | 0.780s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| lc_ctrl_csr_hw_reset | 0.900s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.820s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 17.645s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_same_csr_outstanding | 0.780s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.110s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.110s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_transition_config_regwen | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 5.120s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_sparse | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_sparse | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_bkgn_chk | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_bkgn_chk | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_state_config_sparse | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_kmac_fsm_sparse | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 2 | 2 | 100.00 | |||
| lc_ctrl_state_failure | 6.890s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 5.770s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| lc_ctrl_security_escalation | 5.540s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_main_ctrl_flow_consistency | 2 | 2 | 100.00 | |||
| lc_ctrl_state_post_trans | 2.340s | 0.000us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 6.980s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 3.360s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 3.360s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_token_digest | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_digest | 34.201s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_mux_ctrl_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 4.620s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_mux_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 4.620s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 29.820s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| lc_ctrl_jtag_csr_hw_reset | 37738401729336287931750260518125086395026134548988192813736155429406278917057 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:17 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_jtag_alert_test | 95695719916779087613618452788788775934094273024200642688930791669936973736249 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_csr_aliasing | 66079088253607792395200958001967782563890227720745609357796704084384537244224 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_prog_failure | 97916427802933972128748466847009111110599731098173531879180120066265450290000 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_claim_transition_if | 27759243314852083612469724902892293929731901038362387161013184420386934216907 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_jtag_prog_failure | 105481909950877860521773815940047095446414434044206442034282925005529892910097 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_jtag_access | 113253553301109921104604082447070781415364599111319976887865830317071740087525 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_jtag_regwen_during_op | 109916512130526882398472007010898790800204296535224103431087170561634144701482 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_sec_token_digest | 107652001565829664456421928177492658155757984603918262311641491013443166502164 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl_alert_test | 3467876404711134521479318693067747646190121914331079283584630204123114525291 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| lc_ctrl | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
|
|
| UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| lc_ctrl_stress_all_with_rand_reset | 7563719543470950232927946796756544217993681816005281713922767885402256078297 | 2580 |
UVM_ERROR @ 5650426508 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5650426508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job killed most likely because its dependent job failed. | ||||
| lc_ctrl | None | None | ||