Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.51 %
  • code
  • 73.84 %
  • assert
  • 96.20 %
  • func
  • 38.49 %
  • line
  • 83.58 %
  • branch
  • 94.85 %
  • cond
  • 70.06 %
  • toggle
  • 46.89 %
Validation stages
V1
62.50%
V2
27.50%
V2S
7.14%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
lc_ctrl_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 0.000us 1 1 100.00
csr_rw 0 1 0.00
lc_ctrl_csr_rw 42.468s 0.000us 0 1 0.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.750s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.800s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.750s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
lc_ctrl_csr_rw 42.468s 0.000us 0 1 0.00
lc_ctrl_csr_aliasing 0.800s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 0.000s 0.000us 0 1 0.00
regwen_during_op 0 1 0.00
lc_ctrl_regwen_during_op 0.000s 0.000us 0 1 0.00
rand_wr_claim_transition_if 0 1 0.00
lc_ctrl_claim_transition_if 0.000s 0.000us 0 1 0.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 0.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 0.000s 0.000us 0 1 0.00
security_escalation 0 7 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_errors 0.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 0.000s 0.000us 0 1 0.00
jtag_access 5 13 38.46
lc_ctrl_jtag_csr_hw_reset 1.480s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 13.878s 0.000us 0 1 0.00
lc_ctrl_jtag_csr_bit_bash 9.130s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.150s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.980s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 38.302s 0.000us 0 1 0.00
lc_ctrl_jtag_alert_test 1.730s 0.000us 1 1 100.00
lc_ctrl_jtag_smoke 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_regwen_during_op 0.000s 0.000us 0 1 0.00
jtag_priority 0 1 0.00
lc_ctrl_jtag_priority 0.000s 0.000us 0 1 0.00
lc_ctrl_volatile_unlock 0 1 0.00
lc_ctrl_volatile_unlock_smoke 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
lc_ctrl_stress_all 0.000s 0.000us 0 1 0.00
alert_test 0 1 0.00
lc_ctrl_alert_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 0.000us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
lc_ctrl_csr_hw_reset 0.760s 0.000us 1 1 100.00
lc_ctrl_csr_rw 42.468s 0.000us 0 1 0.00
lc_ctrl_csr_aliasing 0.800s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 34.409s 0.000us 0 1 0.00
tl_d_partial_access 2 4 50.00
lc_ctrl_csr_hw_reset 0.760s 0.000us 1 1 100.00
lc_ctrl_csr_rw 42.468s 0.000us 0 1 0.00
lc_ctrl_csr_aliasing 0.800s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 34.409s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
lc_ctrl_tl_intg_err 1.240s 0.000us 1 1 100.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.240s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 0 1 0.00
lc_ctrl_regwen_during_op 0.000s 0.000us 0 1 0.00
sec_cm_manuf_state_sparse 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_transition_ctr_sparse 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_manuf_state_bkgn_chk 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_transition_ctr_bkgn_chk 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_state_config_sparse 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_main_fsm_sparse 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_kmac_fsm_sparse 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_main_fsm_local_esc 0 2 0.00
lc_ctrl_state_failure 0.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_main_fsm_global_esc 0 1 0.00
lc_ctrl_security_escalation 0.000s 0.000us 0 1 0.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 0.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 0.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 0.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 0.000s 0.000us 0 1 0.00
sec_cm_token_digest 0 1 0.00
lc_ctrl_sec_token_digest 0.000s 0.000us 0 1 0.00
sec_cm_token_mux_ctrl_redun 0 1 0.00
lc_ctrl_sec_token_mux 0.000s 0.000us 0 1 0.00
sec_cm_token_valid_mux_redun 0 1 0.00
lc_ctrl_sec_token_mux 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
default None None
Job timed out after 60 minutes
Job returned non-zero exit code
lc_ctrl_jtag_csr_rw 57461016081008366390302518665852284152755946509854776699995205395935928488271 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 15648889967636006982193028231068826810453184012267562722936957026258562104751 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:18 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_csr_rw 87815085423776805458124924933947746544459977565653473869355952179191886755822 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
lc_ctrl_same_csr_outstanding 77660611870761082862415102139421022867365765782421118343402360383833608800566 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
Job killed most likely because its dependent job failed.
lc_ctrl_smoke 5139046977071508401216084743641900802726607811602096165851806941859615359616 None
lc_ctrl_volatile_unlock_smoke 82142765253035599426956635346980570205765887580298899756833118414099917778004 None
lc_ctrl_state_failure 103913904209364500666326125501325840949384160851722260236971179508609001178943 None
lc_ctrl_state_post_trans 68739916479848149483620907611452747407922423984123532238939519719456480908236 None
lc_ctrl_prog_failure 34703439423594606670318886003963021165463118984385712356469605775153643188238 None
lc_ctrl_errors 6645906627019403442443414019732631299199771325883524358525523523456034681672 None
lc_ctrl_security_escalation 45959916370772092163789021845013743988041872329063619260431404895778722836261 None
lc_ctrl_regwen_during_op 9220933318090057421807601687228974176285511496963848906761226379413282641141 None
lc_ctrl_claim_transition_if 74920651967748298371333066799715035735185044975772567430502543790965457854846 None
lc_ctrl_jtag_smoke 92670887733274987718334120524843724339354915442208079430355528928351175360601 None
lc_ctrl_jtag_state_failure 73430941337875681081150743037067559089873737222253150454379275116478858680325 None
lc_ctrl_jtag_state_post_trans 78041454909961887045649744986102157219843352258965673241364100907895196081648 None
lc_ctrl_jtag_prog_failure 7654753904164499763268438443414411814464118344420447906151779560628457343162 None
lc_ctrl_jtag_errors 65710672748089027290384204630856681978649330225698561865091060637326928868222 None
lc_ctrl_jtag_access 82890206834987822342799543708187046722935901242098542954008789398056694756948 None
lc_ctrl_jtag_priority 76898199299909901328097544851102520972811563351622254882343293886975146754328 None
lc_ctrl_jtag_regwen_during_op 98713761748441839553226568616659889641535667553018866869031200267457460251893 None
lc_ctrl_sec_mubi 90881318532406156895329828684335190573965062554902074272888417121813511434270 None
lc_ctrl_sec_token_mux 66245487112930455103867816496699669549371522077453434827837694733618210347191 None
lc_ctrl_sec_token_digest 92344792997789315262391021650269356830198980712568986138338813666427634815715 None
lc_ctrl_stress_all 46458319391584792868384582316878759393333261191339930435214288285393715956760 None
lc_ctrl_stress_all_with_rand_reset 62144070954306491559163338786473796742563685703033778514581116220359669208526 None
lc_ctrl_sec_cm 76769511908007479516782950480719110609365981021477974451805239046253482923526 None
lc_ctrl_alert_test 6578495478869069129092476677141588113757776982824717728288767366897285178507 None