| V1 |
|
50.00% |
| V2 |
|
50.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_request_test | 2 | 4 | 50.00 | |||
| prim_async_fatal_alert | 0.410s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.460s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_sync_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_alert_test | 2 | 4 | 50.00 | |||
| prim_async_fatal_alert | 0.410s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.460s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_sync_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_alert_ping_request_test | 2 | 4 | 50.00 | |||
| prim_async_fatal_alert | 0.410s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.460s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_sync_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_alert_integrity_errors_test | 2 | 4 | 50.00 | |||
| prim_async_fatal_alert | 0.410s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.460s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_sync_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_init_trigger_test | 2 | 4 | 50.00 | |||
| prim_async_fatal_alert | 0.410s | 0.000us | 1 | 1 | 100.00 | |
| prim_sync_fatal_alert | 0.460s | 0.000us | 1 | 1 | 100.00 | |
| prim_async_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_sync_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| prim_async_fatal_alert_with_3_cycles_skew | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module prim_alert_tb
All of 25 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 4.931 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| prim_alert | None | None |
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-merge_across_libs needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
|
|
| Job timed out after * minutes | ||||
| fatal_alert_with_3_cycles_skew | None | None |
Job timed out after 60 minutes
|
|
| sync_alert | None | None |
Job timed out after 60 minutes
|
|
| Job killed most likely because its dependent job failed. | ||||
| prim_async_alert | 19805092773840921263725982751216175713002265459165912996418228800214661930616 | None | ||
| prim_async_fatal_alert_with_3_cycles_skew | 67060206842336710211261882887371845595418847283584529864713790310254764438863 | None | ||
| prim_sync_alert | 107547566851562022071466732517215129407458295079164726410347375566545677252641 | None | ||
| prim_alert | None | None | ||