Simulation Results: prim_lfsr

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 4 75.00
prim_lfsr_gal_smoke 1.240s 0.000us 1 1 100.00
prim_lfsr_gal_test 176.060s 0.000us 1 1 100.00
prim_lfsr_fib_smoke 1.380s 0.000us 1 1 100.00
prim_lfsr_fib_test 36.277s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
prim_lfsr_fib_test 93541271891693257665853014294065789451496666119944669803023599696655990658102 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:05 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
prim_lfsr None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
Job killed most likely because its dependent job failed.
prim_lfsr None None