Simulation Results: rom_ctrl/32kb

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.41 %
  • code
  • 96.49 %
  • assert
  • 96.80 %
  • func
  • 95.94 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 99.62 %
  • FSM
  • 86.67 %
Validation stages
V1
80.00%
V2
78.57%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.420s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.580s 0.000us 1 1 100.00
csr_rw 0 1 0.00
rom_ctrl_csr_rw 16.094s 0.000us 0 1 0.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.330s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.730s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.110s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
rom_ctrl_csr_rw 16.094s 0.000us 0 1 0.00
rom_ctrl_csr_aliasing 2.730s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.170s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.200s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.890s 0.000us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.950s 0.000us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.020s 0.000us 1 1 100.00
alert_test 0 1 0.00
rom_ctrl_alert_test 13.882s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.410s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.410s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
rom_ctrl_csr_hw_reset 4.580s 0.000us 1 1 100.00
rom_ctrl_csr_rw 16.094s 0.000us 0 1 0.00
rom_ctrl_csr_aliasing 2.730s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.180s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
rom_ctrl_csr_hw_reset 4.580s 0.000us 1 1 100.00
rom_ctrl_csr_rw 16.094s 0.000us 0 1 0.00
rom_ctrl_csr_aliasing 2.730s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
rom_ctrl_passthru_mem_tl_intg_err 68.268s 0.000us 0 1 0.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 92.210s 0.000us 1 1 100.00
rom_ctrl_tl_intg_err 37.980s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 92.210s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 92.210s 0.000us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 92.210s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 92.210s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.420s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.420s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.420s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 37.980s 0.000us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
rom_ctrl_kmac_err_chk 7.020s 0.000us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 36.790s 0.000us 1 1 100.00
sec_cm_ctrl_mem_integrity 0 1 0.00
rom_ctrl_passthru_mem_tl_intg_err 68.268s 0.000us 0 1 0.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 92.210s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 372.710s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
rom_ctrl_alert_test 80331780590756125347046484757476391777473064375087308114648879705633411703847 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_passthru_mem_tl_intg_err 59474747759055228489659616023076153024100277317476468927898565694088651272380 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_csr_rw 66132409430164416075832572992293072302007954462444649541734266802002120868365 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255