Simulation Results: rom_ctrl/64kb

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
80.00%
V2
78.57%
V2S
91.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.930s 0.000us 1 1 100.00
csr_hw_reset 0 1 0.00
rom_ctrl_csr_hw_reset 36.328s 0.000us 0 1 0.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.300s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.800s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rom_ctrl_csr_mem_rw_with_rand_reset 38.341s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.300s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.210s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.080s 0.000us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 17.030s 0.000us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.650s 0.000us 1 1 100.00
alert_test 0 1 0.00
rom_ctrl_alert_test 37.943s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.720s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.720s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
rom_ctrl_csr_hw_reset 36.328s 0.000us 0 1 0.00
rom_ctrl_csr_rw 5.300s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.530s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
rom_ctrl_csr_hw_reset 36.328s 0.000us 0 1 0.00
rom_ctrl_csr_rw 5.300s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 6.030s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.530s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.020s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 207.270s 0.000us 1 1 100.00
rom_ctrl_tl_intg_err 15.894s 0.000us 0 1 0.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 207.270s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 207.270s 0.000us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 207.270s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 207.270s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.930s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.930s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.930s 0.000us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
rom_ctrl_tl_intg_err 15.894s 0.000us 0 1 0.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
rom_ctrl_kmac_err_chk 13.650s 0.000us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 70.620s 0.000us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.020s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 207.270s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 13.881s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
rom_ctrl_stress_all_with_rand_reset 51928449730958136644808795751522424925324966968080432318699843480589673790953 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_alert_test 43952582416990934429459540477861641641286416795306317060535050254898291603163 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_tl_intg_err 7364877294252657852665704895421307181462888496839465538116899735072527100269 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_csr_hw_reset 16554485367580180307798585011728193248398482971429063860433381927337086243895 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl_csr_mem_rw_with_rand_reset 36795515070081372566059607942314897186390536600570437480737533184656304940830 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
rom_ctrl None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
Job killed most likely because its dependent job failed.
rom_ctrl None None