| V1 |
|
75.00% |
| V2 |
|
84.21% |
| V2S |
|
81.82% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rstmgr_smoke | 1.050s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 0.960s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rstmgr_csr_rw | 56.246s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 1.990s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 1.100s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.360s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| rstmgr_csr_rw | 56.246s | 0.000us | 0 | 1 | 0.00 | |
| rstmgr_csr_aliasing | 1.100s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 1 | 1 | 100.00 | |||
| rstmgr_por_stretcher | 1.080s | 0.000us | 1 | 1 | 100.00 | |
| sw_rst | 0 | 1 | 0.00 | |||
| rstmgr_sw_rst | 58.353s | 0.000us | 0 | 1 | 0.00 | |
| sw_rst_reset_race | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 0.750s | 0.000us | 1 | 1 | 100.00 | |
| reset_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.150s | 0.000us | 1 | 1 | 100.00 | |
| cpu_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.150s | 0.000us | 1 | 1 | 100.00 | |
| alert_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.150s | 0.000us | 1 | 1 | 100.00 | |
| reset_info_capture | 1 | 1 | 100.00 | |||
| rstmgr_reset | 4.150s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rstmgr_stress_all | 14.660s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rstmgr_alert_test | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 2.230s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 2.230s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| rstmgr_csr_hw_reset | 0.960s | 0.000us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 56.246s | 0.000us | 0 | 1 | 0.00 | |
| rstmgr_csr_aliasing | 1.100s | 0.000us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 0.930s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| rstmgr_csr_hw_reset | 0.960s | 0.000us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 56.246s | 0.000us | 0 | 1 | 0.00 | |
| rstmgr_csr_aliasing | 1.100s | 0.000us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 0.930s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rstmgr_tl_intg_err | 2.270s | 0.000us | 1 | 1 | 100.00 | |
| rstmgr_sec_cm | 21.040s | 0.000us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 21.040s | 0.000us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 21.040s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rstmgr_tl_intg_err | 2.270s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_scan_intersig_mubi | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 0.970s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_shadow | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.830s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 21.040s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 0 | 1 | 0.00 | |||
| rstmgr_csr_rw | 56.246s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dump_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| rstmgr_csr_rw | 56.246s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| rstmgr_csr_rw | 31373173057840451926962372439621365282461483061923097893576210350244490596740 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:05 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rstmgr_sw_rst | 53167704479641563124431869722148675084083343479631028130991845699802941282530 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:07 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rstmgr | None | None |
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-elfile needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|