| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rstmgr_cnsty_chk_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module tb
All of 43 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 6.569 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| rstmgr_cnsty_chk_test | 104866936657779338382903631128157471652710468180422311996261794052728170725502 | None | ||
| rstmgr_cnsty_chk | None | None | ||
| rstmgr_cnsty_chk | None | None | ||