| V1 |
|
32.26% |
| V2 |
|
25.00% |
| V2S |
|
58.33% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 32.239s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_hw_reset | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_rw | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_bit_bash | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_aliasing | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_csr_hw_reset | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_csr_rw | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_csr_bit_bash | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_csr_aliasing | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_cmderr_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_not_supported | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_not_supported | 0.770s | 0.000us | 1 | 1 | 100.00 | |
| cmderr_exception | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_exception | 11.852s | 0.000us | 0 | 1 | 0.00 | |
| mem_tl_access_resuming | 0 | 1 | 0.00 | |||
| rv_dm_mem_tl_access_resuming | 0.630s | 0.000us | 0 | 1 | 0.00 | |
| mem_tl_access_halted | 1 | 1 | 100.00 | |||
| rv_dm_mem_tl_access_halted | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| cmderr_halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_halt_resume | 2.180s | 0.000us | 1 | 1 | 100.00 | |
| dataaddr_rw_access | 1 | 1 | 100.00 | |||
| rv_dm_dataaddr_rw_access | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_halt_resume_whereto | 1.490s | 0.000us | 1 | 1 | 100.00 | |
| progbuf_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| abstractcmd_status | 1 | 1 | 100.00 | |||
| rv_dm_abstractcmd_status | 0.880s | 0.000us | 1 | 1 | 100.00 | |
| progbuf_read_write_execute | 1 | 1 | 100.00 | |||
| rv_dm_progbuf_read_write_execute | 0.860s | 0.000us | 1 | 1 | 100.00 | |
| progbuf_exception | 0 | 1 | 0.00 | |||
| rv_dm_cmderr_exception | 11.852s | 0.000us | 0 | 1 | 0.00 | |
| rom_read_access | 1 | 1 | 100.00 | |||
| rv_dm_rom_read_access | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rv_dm_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rv_dm_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rv_dm_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rv_dm_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| rv_dm_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| rv_dm_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 32.239s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dtm_hard_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_hard_reset | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dtm_idle_hint | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_idle_hint | 1.790s | 0.000us | 1 | 1 | 100.00 | |
| jtag_dmi_failed_op | 0 | 1 | 0.00 | |||
| rv_dm_dmi_failed_op | 11.927s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_dm_inactive | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 0.890s | 0.000us | 1 | 1 | 100.00 | |
| sba | 0 | 2 | 0.00 | |||
| rv_dm_sba_tl_access | 157.440s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 36.372s | 0.000us | 0 | 1 | 0.00 | |
| bad_sba | 0 | 1 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 157.920s | 0.000us | 0 | 1 | 0.00 | |
| sba_autoincrement | 0 | 1 | 0.00 | |||
| rv_dm_autoincr_sba_tl_access | 127.630s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_debug_disabled | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 1.180s | 0.000us | 0 | 1 | 0.00 | |
| sba_debug_disabled | 1 | 1 | 100.00 | |||
| rv_dm_sba_debug_disabled | 2.380s | 0.000us | 1 | 1 | 100.00 | |
| ndmreset_req | 1 | 1 | 100.00 | |||
| rv_dm_ndmreset_req | 0.790s | 0.000us | 1 | 1 | 100.00 | |
| hart_unavail | 0 | 1 | 0.00 | |||
| rv_dm_hart_unavail | 11.925s | 0.000us | 0 | 1 | 0.00 | |
| tap_ctrl_transitions | 0 | 2 | 0.00 | |||
| rv_dm_tap_fsm | 13.818s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hartsel_warl | 1 | 1 | 100.00 | |||
| rv_dm_hartsel_warl | 0.740s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rv_dm_stress_all | 1.110s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_dm_alert_test | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rv_dm_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rv_dm_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| rv_dm_sec_cm | 1.430s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rv_dm_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 2.380s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 2.380s | 0.000us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 32.239s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.050s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_exec_ctrl_mubi | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.050s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 13.420s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rv_dm_scanmode | 485.160s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 101 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 18.529 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| rv_dm_smoke | 17378200313586155840566255825208261092052680803604940647296913983845483054479 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_tap_fsm | 19671078219876769280019547983429865972918145122757323976967816858486717966412 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_delayed_resp_sba_tl_access | 75026736386639500797376488971780099551566858202306764172721713486731976607870 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_cmderr_exception | 39717870035686892131803531640452284074037270075387647574834967946786837695081 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_hart_unavail | 57288101537041638864433068644082874551127826632328435357835274352928651407635 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm_dmi_failed_op | 30296945858375808863938089388299922464603804700546140602767320544375849950756 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:06 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| rv_dm | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| rv_dm_sba_tl_access | 113175036576323371561143151383304672986020224701792482756184409400695616237643 | 86 |
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_bad_sba_tl_access | 68831161701117645184136745151799371032978594847879416629367519128379952309442 | 86 |
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_autoincr_sba_tl_access | 101190944206694560720065906771706242378276742535234979907669611958004254653741 | 86 |
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_scanmode | 79804625936492557338063363496021745696264441522381104294792691146513089609628 | 77 |
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*]) | ||||
| rv_dm_mem_tl_access_resuming | 20764225767897301045327727436861411533397111189365140773623445658194261498946 | 77 |
UVM_ERROR @ 108043106 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 108043106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_dm_stress_all | 48336848845745113466348214146967725852454305028734183999823007023312292891096 | 81 |
UVM_ERROR @ 1237667398 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1237667398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) | ||||
| rv_dm_jtag_dmi_debug_disabled | 65668997627730576524771295495523081486811472641502425114147233588357802665554 | 77 |
UVM_ERROR @ 446211415 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (853009124 [0x32d7e2e4] vs 0 [0x0])
UVM_INFO @ 446211415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| rv_dm_sparse_lc_gate_fsm | 8097072416222942649802643146871578803381311571799629977983630753621831969175 | None |
Job timed out after 60 minutes
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done) | ||||
| rv_dm_stress_all_with_rand_reset | 68361873011645527264288172325600037938064889863089010898744175412880199989371 | 103 |
UVM_FATAL @ 12987168720 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 12987168720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job killed most likely because its dependent job failed. | ||||
| rv_dm_csr_aliasing | 75997268174025583689918459914724091577107577563728674128462491337515053114869 | None | ||
| rv_dm_jtag_dtm_csr_hw_reset | 41105658507649988418023230886494975907383258183134404568307642311328195130895 | None | ||
| rv_dm_jtag_dtm_csr_rw | 87020701189344610611475274505957557000700413737205868471077097371074218056873 | None | ||
| rv_dm_jtag_dtm_csr_bit_bash | 30763289691377947074993386869079175668945423326128498752590115536872487432464 | None | ||
| rv_dm_jtag_dtm_csr_aliasing | 64038948674748165080495445773985110872161051973046489993716487496220675639992 | None | ||
| rv_dm_jtag_dmi_csr_hw_reset | 76401274748724217456907862995161488951759497183795668063043888861268495453928 | None | ||
| rv_dm_jtag_dmi_csr_rw | 111560820808209262286622451553217889363799699126949005750816955836393923960303 | None | ||
| rv_dm_jtag_dmi_csr_bit_bash | 84892608682742051251092823130953774509621313371123742351917464213828423991352 | None | ||
| rv_dm_jtag_dmi_csr_aliasing | 75479545693282555530454372523394515367143523353122795269845000097966698811617 | None | ||
| rv_dm_tap_fsm_rand_reset | 81817157286506701349885654752808978006146839796562552044995104650186693529139 | None | ||
| rv_dm_tl_errors | 78149823003259123190062676925189976483405455081667705484479269796584079475726 | None | ||
| rv_dm_tl_intg_err | 23137720800653605336158633603762949373780391236673230817828591018072370380720 | None | ||
| rv_dm_mem_walk | 30416060190891858376640127654968600426945895340118484592704153018164197390970 | None | ||
| rv_dm_mem_partial_access | 2165958201074646439380985748366695301768391401533112515127828581094466437786 | None | ||
| rv_dm_csr_hw_reset | 59556473529681555144852488739044988481019911701250856401206411972647456724558 | None | ||
| rv_dm_csr_rw | 49266694172034883713236970450399624289742108298207357594614418142590184566070 | None | ||
| rv_dm_csr_bit_bash | 19281222740530381699499171175501671430352654038497342330620132904751376929365 | None | ||
| rv_dm_same_csr_outstanding | 5211948656057147115001817866991412253946021702985954206156105667027516920917 | None | ||
| rv_dm_csr_mem_rw_with_rand_reset | 87684404126252634264540125545554016202705213748057721780742663467716763650326 | None | ||
| rv_dm | None | None | ||