| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 0 | 1 | 0.00 | |||
| rv_timer_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rv_timer_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rv_timer_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disabled | 0 | 1 | 0.00 | |||
| rv_timer_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cfg_update_on_fly | 0 | 1 | 0.00 | |||
| rv_timer_cfg_update_on_fly | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| no_interrupt_test | 0 | 1 | 0.00 | |||
| rv_timer_cfg_update_on_fly | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress | 0 | 1 | 0.00 | |||
| rv_timer_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rv_timer_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| rv_timer_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_timer_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_timer_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rv_timer_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rv_timer_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| rv_timer_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rv_timer_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 1 | 0.00 | |||
| rv_timer_min | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | ||||
| default | None | None |
Job timed out after 60 minutes
|
|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 68 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 12.605 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| rv_timer_tl_errors | 53331038111342914514680545185147218030859116883742022585530737324605409276640 | None | ||
| rv_timer_tl_intg_err | 76233327074700609157827463207025670296087345281774047372364706700291766678519 | None | ||
| rv_timer_intr_test | 44786686592475886403850717752638234293281196186881385241418631893197979580939 | None | ||
| rv_timer_csr_hw_reset | 68852779068141067652816286273691379535883904661798624836971559502994185630785 | None | ||
| rv_timer_csr_rw | 111908247576106244147549356224688723943004294127022976044139850612552293461250 | None | ||
| rv_timer_csr_bit_bash | 91752936870507420727217980454426824528968149263862471318360619626920270920820 | None | ||
| rv_timer_csr_aliasing | 75954241044479121577225657193181144391402912458359317202236571240747375905824 | None | ||
| rv_timer_same_csr_outstanding | 114468175700680318896491664910267153688839891413896901957753840089217245732089 | None | ||
| rv_timer_csr_mem_rw_with_rand_reset | 76305074864790047796803410507781412944343917942074421502270833670014622650306 | None | ||
| rv_timer_random | 69629607849972599411728791127387160524917877704390912743723264369787218893662 | None | ||
| rv_timer_min | 37184638262503777494619369453657461160453243761519304135334698998458731643176 | None | ||
| rv_timer_max | 1975160922083051681422224938723931575391561195441882712747249307255615182426 | None | ||
| rv_timer_disabled | 90254346798848748844939144031173646190245435711467772631331835497835409110107 | None | ||
| rv_timer_cfg_update_on_fly | 19779961462713250470029774790006312882166188499282852377544225552703376808473 | None | ||
| rv_timer_random_reset | 109414789888321892457424390507417643686618252395095674453862880857844631185550 | None | ||
| rv_timer_stress_all_with_rand_reset | 109948640242668092785359065566601647626903913196499194114404517398734521049902 | None | ||
| rv_timer_stress_all | 90097218106247602572089036468403738313261782994376436141881310522746576631457 | None | ||
| rv_timer_sec_cm | 23657102996203539430061676028773638057077080498195278750645576066184185282535 | None | ||
| rv_timer_alert_test | 108700794105171625790109929000504994720296801837668458864085314224000300054923 | None | ||
| rv_timer | None | None | ||
| rv_timer | None | None | ||