| V1 |
|
80.00% |
| V2 |
|
82.69% |
| V2S |
|
33.33% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 44.520s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| spi_device_csr_hw_reset | 11.912s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_device_csr_rw | 1.090s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 8.150s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 5.500s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 1.330s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_device_csr_rw | 1.090s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 5.500s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| spi_device_mem_walk | 40.401s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.320s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.720s | 0.000us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.630s | 0.000us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 58.759s | 0.000us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 0.950s | 0.000us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 0.950s | 0.000us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 1.670s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.710s | 0.000us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 0 | 1 | 0.00 | |||
| spi_device_tpm_all | 19.634s | 0.000us | 0 | 1 | 0.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 4.620s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 15.090s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 15.090s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 8.670s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 8.670s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 8.670s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 8.670s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 8.670s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 1.890s | 0.000us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 1.710s | 0.000us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 1.710s | 0.000us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 1.710s | 0.000us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 4.220s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 5.030s | 0.000us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 1.710s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 116.140s | 0.000us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 0 | 1 | 0.00 | |||
| spi_device_cfg_cmd | 36.279s | 0.000us | 0 | 1 | 0.00 | |
| write_enable_disable | 0 | 1 | 0.00 | |||
| spi_device_cfg_cmd | 36.279s | 0.000us | 0 | 1 | 0.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 44.520s | 0.000us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 12.510s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 160.550s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| spi_device_alert_test | 33.934s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| spi_device_intr_test | 36.216s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.470s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.470s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| spi_device_csr_hw_reset | 11.912s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_rw | 1.090s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 5.500s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 2.750s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| spi_device_csr_hw_reset | 11.912s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_rw | 1.090s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 5.500s | 0.000us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 2.750s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| spi_device_tl_intg_err | 17.925s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_sec_cm | 0.840s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| spi_device_tl_intg_err | 17.925s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 57.970s | 0.000us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| spi_device_tl_intg_err | 113920741139368997562859314297774767422544638591105897904231633164585667012233 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_intr_test | 100444531573247098771351609758870013518018691278506888764226387742254582873165 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_mem_walk | 22818539292554060046180275919172108789898624408755880720077679026202540052058 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_csr_hw_reset | 22718545112495976357601717780377842427867525899862414686904890928382763067457 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_ram_cfg | 37524760463861836469396785403551480650602930896051818226469971212731600357108 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_tpm_all | 41277851505319100692681379087223267079135809223445264224545310709797849257569 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_cfg_cmd | 98047862594149283636018745056653987892051168874597625081265175428622822703462 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:19 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device_alert_test | 100482760849591762156594653749094378105841102944474512403905677865371452759689 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:20 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| spi_device | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | ||||
| spi_device_mem_parity | 35781669442415602297299903614590508150881109576355193749828200114627815847170 | 76 |
UVM_ERROR @ 3183536 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[104])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3183536 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3183536 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|