| V1 |
|
80.00% |
| V2 |
|
80.00% |
| V2S |
|
66.67% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 9.980s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 1.310s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.230s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sram_ctrl_csr_rw | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| sram_ctrl_mem_walk | 39.974s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| sram_ctrl_mem_partial_access | 9.877s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 1 | 1 | 100.00 | |||
| sram_ctrl_multiple_keys | 209.740s | 0.000us | 1 | 1 | 100.00 | |
| stress_pipeline | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_pipeline | 112.140s | 0.000us | 1 | 1 | 100.00 | |
| bijection | 1 | 1 | 100.00 | |||
| sram_ctrl_bijection | 1330.230s | 0.000us | 1 | 1 | 100.00 | |
| access_during_key_req | 1 | 1 | 100.00 | |||
| sram_ctrl_access_during_key_req | 476.610s | 0.000us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 60.560s | 0.000us | 1 | 1 | 100.00 | |
| executable | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 329.100s | 0.000us | 1 | 1 | 100.00 | |
| partial_access | 2 | 2 | 100.00 | |||
| sram_ctrl_partial_access | 29.530s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_partial_access_b2b | 282.140s | 0.000us | 1 | 1 | 100.00 | |
| max_throughput | 1 | 3 | 33.33 | |||
| sram_ctrl_max_throughput | 36.325s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_throughput_w_partial_write | 11.957s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_throughput_w_readback | 35.780s | 0.000us | 1 | 1 | 100.00 | |
| regwen | 0 | 1 | 0.00 | |||
| sram_ctrl_regwen | 32.147s | 0.000us | 0 | 1 | 0.00 | |
| ram_cfg | 1 | 1 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.160s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all | 9.864s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| sram_ctrl_alert_test | 60.345s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 3.400s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 3.400s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.670s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.640s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.620s | 0.000us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.670s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 28.260s | 0.000us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| sram_ctrl_sec_cm | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| sram_ctrl_tl_intg_err | 1.250s | 0.000us | 1 | 1 | 100.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_intg_err | 1.250s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| sram_ctrl_regwen | 32.147s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_readback_config_regwen | 0 | 1 | 0.00 | |||
| sram_ctrl_regwen | 32.147s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_exec_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.600s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 329.100s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_exec_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 329.100s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 329.100s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 60.560s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 3.430s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 28.260s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_mem_readback | 1 | 1 | 100.00 | |||
| sram_ctrl_readback_err | 3.450s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 9.980s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_addr_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 9.980s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 329.100s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_global_esc | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 60.560s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_key_local_esc | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_init_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 9.980s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.590s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 9.857s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| sram_ctrl_max_throughput | 78390164751798585850669267286029169306653282325517418074632486378943643483233 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_throughput_w_partial_write | 28868410414316103962424120970518465848900768153505462008714482201827478118649 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_regwen | 5795976911846904024214231100664037331039127122604456568766041256466122397193 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_mem_walk | 31066913136810924068434881901245523899163476367491858194872887070803253173534 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_mem_partial_access | 54898391532620718954734381015254541814152814564448077807988904350009791344750 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_stress_all_with_rand_reset | 70805728201568485091925848338433421054576957967673624858708737706066569264984 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_stress_all | 1112140838459411104185775514187649430236660164682063905748697353167338242965 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl_alert_test | 24642061658618761578925813190120597343590925228153210287837107821601942826078 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| sram_ctrl | None | None |
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
|
|
| Offending '(!$isunknown(rdata_o))' | ||||
| sram_ctrl_sec_cm | 12913604770643373236919682001334364467739634184872805573823948682046908336977 | 99 |
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1899831 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1899831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|