Simulation Results: sram_ctrl/ret

 
19/03/2026 16:03:37 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
90.00%
V2
68.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 11.410s 0.000us 1 1 100.00
csr_hw_reset 0 1 0.00
sram_ctrl_csr_hw_reset 11.989s 0.000us 0 1 0.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.660s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.010s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.420s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.660s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.070s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.920s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 456.670s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 217.360s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 51.380s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 227.660s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.300s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 727.120s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 33.800s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 412.360s 0.000us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 37.913s 0.000us 0 1 0.00
sram_ctrl_throughput_w_partial_write 39.931s 0.000us 0 1 0.00
sram_ctrl_throughput_w_readback 16.068s 0.000us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 725.880s 0.000us 1 1 100.00
ram_cfg 0 1 0.00
sram_ctrl_ram_cfg 36.251s 0.000us 0 1 0.00
stress_all 1 1 100.00
sram_ctrl_stress_all 615.060s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.630s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.080s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.080s 0.000us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
sram_ctrl_csr_hw_reset 11.989s 0.000us 0 1 0.00
sram_ctrl_csr_rw 0.660s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 18.152s 0.000us 0 1 0.00
tl_d_partial_access 2 4 50.00
sram_ctrl_csr_hw_reset 11.989s 0.000us 0 1 0.00
sram_ctrl_csr_rw 0.660s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 18.152s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 0 1 0.00
sram_ctrl_passthru_mem_tl_intg_err 0.000s 0.000us 0 1 0.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.600s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 1.790s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.600s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.790s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 725.880s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 725.880s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.660s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 727.120s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 727.120s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 727.120s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.300s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.740s 0.000us 1 1 100.00
sec_cm_mem_integrity 0 1 0.00
sram_ctrl_passthru_mem_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.910s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 11.410s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 11.410s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 727.120s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.600s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.300s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.600s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.600s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 11.410s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.600s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.650s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
sram_ctrl_max_throughput 8704901490971634409556953103420391213820784354627861231286337738654923213638 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_throughput_w_partial_write 36231205670425519724355094975361280524774575300438116652917257366549385495113 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_throughput_w_readback 31684203075611735668134988933684506616191985097353878689371284755771943569385 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:08 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_ram_cfg 88510971354337150054868620335854198402006388660335755828301391932166810973713 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:09 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_csr_hw_reset 65510118287043038735028947784281045814156065533249377895033755476330737703607 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:09 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl_same_csr_outstanding 47257961341515950980893512438627161969060245985580523562775239308391691416311 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 19 16:09 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
sram_ctrl None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 113773995425251085751939592304389005666278273918453187913389632029404406532548 101
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 15124358 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 15124358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
sram_ctrl_passthru_mem_tl_intg_err 58973200533163896855867492817108802306180698569120470509047341686159987794761 None
Job timed out after 60 minutes
Job killed most likely because its dependent job failed.
sram_ctrl None None