Simulation Results: clkmgr

 
23/03/2026 16:04:27 DVSim: v1.16.0 sha: 7fd2965 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.45 %
  • code
  • 69.56 %
  • assert
  • 89.05 %
  • func
  • 67.75 %
  • line
  • 82.39 %
  • branch
  • 87.58 %
  • cond
  • 78.87 %
  • toggle
  • 98.96 %
  • FSM
  • 0.00 %
Validation stages
V1
87.50%
V2
68.42%
V2S
70.59%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.070s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.030s 0.000us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.440s 0.000us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.280s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.570s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
clkmgr_csr_aliasing 1.280s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.890s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.840s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.020s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.070s 0.000us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.830s 0.000us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.810s 0.000us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.830s 0.000us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.850s 0.000us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.010s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.370s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.370s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 1.030s 0.000us 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
clkmgr_csr_aliasing 1.280s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 0.700s 0.000us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 1.030s 0.000us 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
clkmgr_csr_aliasing 1.280s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 0.700s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.310s 0.000us 1 1 100.00
clkmgr_tl_intg_err 0.710s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.630s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.710s 0.000us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.830s 0.000us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.810s 0.000us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.060s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.310s 0.000us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.310s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.620s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.780s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 17791758584516977479412096976415691330329654336677311478585788703693522970122 76
UVM_ERROR @ 6406379 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 6406379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 58682811980079814916555640657453555024007995575612029552162647035880261864613 75
UVM_ERROR @ 7906758 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 7906758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 107378290875703828744612900106600330677945850113807360728809059685864887607338 78
UVM_ERROR @ 8697790 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 8697790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 87381348588743327897544857751928098377704401023133496009024757739050423783315 79
UVM_ERROR @ 79131456 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 79131456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 71087644202749794802749941584711236044216781829819981197433030606176503460001 74
UVM_ERROR @ 2883485 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
UVM_INFO @ 2883485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 58499390038647476620515040563098531422959911459805070583658372221893600142229 75
UVM_ERROR @ 4056611 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 4056611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_tl_intg_err 38253317632270119157426052855325609780030047288900922170385218384063779369037 85
UVM_ERROR @ 5790761 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 5790761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 78818076057151471175667811478363403210812545948930761654657831571710864287903 75
UVM_ERROR @ 233944368 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 233944368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 69376460384522609063535735613384276460605619601471503980379022502220008590672 75
UVM_ERROR @ 1938071 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x17269f24 read out mismatch
UVM_INFO @ 1938071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---