Simulation Results: i2c

 
23/03/2026 16:04:27 DVSim: v1.16.0 sha: 7fd2965 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.00 %
  • code
  • 81.64 %
  • assert
  • 96.19 %
  • func
  • 77.17 %
  • line
  • 96.41 %
  • branch
  • 92.41 %
  • cond
  • 85.27 %
  • toggle
  • 89.45 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 20.490s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.480s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.690s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.380s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.750s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.620s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 86.910s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 22.680s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.640s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 44.450s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 59.100s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.840s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 5.930s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 6.350s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 77.670s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.560s 0.000us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.890s 0.000us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.110s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 209.720s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.980s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 14.180s 0.000us 1 1 100.00
i2c_target_intr_smoke 2.650s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.760s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 0.840s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 3.450s 0.000us 1 1 100.00
i2c_target_stress_rd 14.180s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 1.090s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.100s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 5.130s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.030s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 16.400s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.050s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.230s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 22.680s 0.000us 1 1 100.00
i2c_host_perf_precise 2.140s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.560s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.080s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.700s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.700s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.060s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.570s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.500s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.620s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.620s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.290s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.290s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.690s 0.000us 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.760s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.690s 0.000us 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 1.370s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.760s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.750s 0.000us 1 1 100.00
i2c_tl_intg_err 1.490s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.490s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 19.100s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.780s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 6.380s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 103863536860431760186578688035498815897683950720045675617919978774129790665245 86
UVM_ERROR @ 22045317 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 22045317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 63277579829217585859962079643257859841821926362536525576534386532444080977001 101
UVM_ERROR @ 6583926156 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 6583926156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 55938304449622129350292891127996399405758491877775617768692323451504795900895 84
UVM_ERROR @ 848295786 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 848295786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 91635093730078907055192371647332619524424778605403212986756883129496178816251 78
UVM_ERROR @ 56307543 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 114 [0x72])
UVM_INFO @ 56307543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 71169956193015350658746913422378453872116610750750799438789365340825333691157 79
UVM_FATAL @ 10270115197 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10270115197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 46135300443156260542405244090713831401843023669023363816841821473983961657658 101
UVM_ERROR @ 618047734 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 618047734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 40247521342952054843763275272450433711130328500023184800164439327159426363825 86
UVM_ERROR @ 2219088521 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2219088521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---