Simulation Results

Simulation Results: keymgr_dpe

23/03/2026 16:04:27 DVSim: v1.16.0 sha: 7fd2965 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.76 %

code
83.87 %

assert
97.64 %

func
15.76 %

line
97.38 %

branch
94.42 %

cond
88.76 %

toggle
63.09 %

FSM
75.68 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	12.150s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	1.040s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	0.920s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	3.150s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	3.740s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	1.790s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	0.920s	0.000us	1	1	100.00
	keymgr_dpe_csr_aliasing	3.740s	0.000us	1	1	100.00

V2

12/12 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	0.930s	0.000us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	0.940s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	1.410s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	1.410s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	1.040s	0.000us	1	1	100.00
	keymgr_dpe_csr_rw	0.920s	0.000us	1	1	100.00
	keymgr_dpe_csr_aliasing	3.740s	0.000us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.020s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	1.040s	0.000us	1	1	100.00
	keymgr_dpe_csr_rw	0.920s	0.000us	1	1	100.00
	keymgr_dpe_csr_aliasing	3.740s	0.000us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.020s	0.000us	1	1	100.00

V2S

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	10.020s	0.000us	1	1	100.00
	keymgr_dpe_tl_intg_err	6.100s	0.000us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	1.520s	0.000us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	1.520s	0.000us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	1.520s	0.000us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	1.520s	0.000us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	2.260s	0.000us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	10.020s	0.000us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	10.020s	0.000us	1	1	100.00