Simulation Results: kmac/unmasked

 
23/03/2026 16:04:27 DVSim: v1.16.0 sha: 7fd2965 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.80 %
  • code
  • 88.01 %
  • assert
  • 97.75 %
  • func
  • 92.64 %
  • line
  • 97.22 %
  • branch
  • 94.86 %
  • cond
  • 90.10 %
  • toggle
  • 100.00 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 40.570s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.830s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.730s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.690s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.310s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
kmac_csr_aliasing 3.690s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.790s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1448.230s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 109.660s 0.000us 1 1 100.00
test_vectors 7 8 87.50
kmac_test_vectors_sha3_224 1769.360s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 21.040s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 14.110s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 12.320s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 135.610s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 204.110s 0.000us 1 1 100.00
kmac_test_vectors_kmac 1.810s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 53.559s 0.000us 0 1 0.00
sideload 1 1 100.00
kmac_sideload 171.850s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 47.060s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 14.590s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 241.680s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 211.520s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.560s 0.000us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 20.030s 0.000us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 23.660s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 16.330s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 15.850s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.110s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 150.580s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.680s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.750s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.240s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.240s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.830s 0.000us 1 1 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
kmac_csr_aliasing 3.690s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.940s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.830s 0.000us 1 1 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
kmac_csr_aliasing 3.690s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.940s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.240s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.240s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.240s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.240s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.780s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 3.510s 0.000us 1 1 100.00
kmac_sec_cm 22.760s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.510s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.110s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 40.570s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 171.850s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.240s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 22.760s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 22.760s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 22.760s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 40.570s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.110s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 22.760s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 153.130s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 40.570s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 48.740s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 80973901730436088676042009407990353348941828650515758047802402772669225642490 78
UVM_FATAL @ 10033680855 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf009c000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10033680855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
kmac_test_vectors_kmac_xof 82963043728471492937746566169950268150149104210898644079429005755114901289322 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 23 16:07 2026
Feature removed during lmreread, or wrong
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Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 106980751681610763797288202288725205795057482932206321495092904517167276403437 335
UVM_ERROR @ 2934990889 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2934990889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---