Simulation Results: mbx

 
23/03/2026 16:04:27 DVSim: v1.16.0 sha: 7fd2965 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.03 %
  • code
  • 91.44 %
  • assert
  • 96.38 %
  • func
  • 76.26 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 85.73 %
Validation stages
V1
87.50%
V2
75.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 53.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 4.000s 0.000us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 3.000s 0.000us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 26.000s 0.000us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 3.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 2.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 2.000s 0.000us 1 1 100.00
mbx_tl_intg_err 3.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed
mbx_stress 109722936777946173055402451173820412518714403561692641530033134268803081672427 179
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 33994903 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 33994903 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 33994903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 51206284229184314816804033204831211063274302571898327384237409344770326280484 95
UVM_ERROR @ 46612025 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 46612025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 35338810505210413502563900881124009920222914146186651087097182111620423307638 85
UVM_ERROR @ 6539771 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15900) { a_addr: 'hdce7d3d4 a_data: 'h6f05564f a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h1 a_user: 'h24028 d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6539771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 9495465636197160768799196723096833246390147164410849459324433393326599743074 86
UVM_ERROR @ 1852973 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@17685) { a_addr: 'hcf9b3454 a_data: 'hdf08e414 a_mask: 'h5 a_size: 'h2 a_param: 'h0 a_source: 'h78 a_opcode: 'h1 a_user: 'h26910 d_param: 'h0 d_source: 'h78 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1852973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---