Simulation Results

Simulation Results: rv_dm/use_dmi_interface

23/03/2026 16:04:27 DVSim: v1.16.0 sha: 7fd2965 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.42 %

code
73.54 %

assert
96.09 %

func
71.63 %

line
90.16 %

branch
74.57 %

cond
76.04 %

toggle
70.66 %

FSM
56.25 %

Validation stages

V1		96.77%
V2		75.00%
V2S		100.00%
V3		0.00%
unmapped		0.00%

30/31 passed

96.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	3.140s	0.000us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.440s	0.000us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.750s	0.000us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	9.690s	0.000us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.290s	0.000us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	5.340s	0.000us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	7.890s	0.000us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	67.950s	0.000us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	62.210s	0.000us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.010s	0.000us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.370s	0.000us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.700s	0.000us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.950s	0.000us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	1.020s	0.000us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	2.570s	0.000us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.900s	0.000us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.600s	0.000us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.010s	0.000us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.810s	0.000us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	1.670s	0.000us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.700s	0.000us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.840s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	2.010s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	2.250s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	19.740s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	54.330s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	2.210s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	54.330s	0.000us	1	1	100.00
	rv_dm_csr_rw	2.250s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.860s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	1.110s	0.000us	1	1	100.00

21/28 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	3.140s	0.000us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.730s	0.000us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	1.550s	0.000us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	1.200s	0.000us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.790s	0.000us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	199.140s	0.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	257.580s	0.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	274.760s	0.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	270.170s	0.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	1.110s	0.000us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	1.190s	0.000us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	0.980s	0.000us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.830s	0.000us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	6.720s	0.000us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	27.850s	0.000us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.700s	0.000us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	2.220s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.930s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	1.720s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	1.720s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	54.330s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	2.010s	0.000us	1	1	100.00
	rv_dm_csr_rw	2.250s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	5.850s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	54.330s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	2.010s	0.000us	1	1	100.00
	rv_dm_csr_rw	2.250s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	5.850s	0.000us	1	1	100.00

V2S

12/12 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	1.680s	0.000us	1	1	100.00
	rv_dm_tl_intg_err	7.070s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	7.070s	0.000us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	1.190s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.850s	0.000us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	1.190s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.850s	0.000us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	3.140s	0.000us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	1.460s	0.000us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.770s	0.000us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.770s	0.000us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	1.460s	0.000us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	4.150s	0.000us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	285.220s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	4283979235127638634186750829933254938031834686522545775372920671871441934365	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	46637965196641051936410290569550013898258199397460196346110560222388593232939	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	27324641822270778801807902160617410839992300139817860071413277530523944467200	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	91373436569370567838608569358747471942457669090147420797987374317760484059818	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	81084838563219084302018530065722737059339438817516732238703758963936224636177	77	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	61861850532369238954245345954298571157793163591825208423639958890499246600862	77	UVM_ERROR @ 149382967 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 149382967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	95723584045966638695738980909016240777553075380135464736718866991516634295966	83	UVM_ERROR @ 779934862 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 779934862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	86255292653093475369291709239230945979791817072292740637754607023315208732823	77	UVM_ERROR @ 45574532 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 45574532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	115740509788695647588297973443116079501966843595588770338750420854411982303731	77	UVM_ERROR @ 157428005 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3764235762 [0xe05dadf2] vs 0 [0x0]) UVM_INFO @ 157428005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	11770933373284196784091682118771198135770751035523314052541887159691089880238	79	UVM_ERROR @ 751927012 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1313717715 [0x4e4dbdd3] vs 0 [0x0]) UVM_INFO @ 751927012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---