Simulation Results: dma

 
24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.99 %
  • code
  • 92.20 %
  • assert
  • 95.76 %
  • func
  • 64.00 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 0.000us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 0.000us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 0.000us 1 1 100.00
dma_csr_aliasing 4.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 63.000s 0.000us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 450.000s 0.000us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 118.000s 0.000us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 118.000s 0.000us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 450.000s 0.000us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 115.000s 0.000us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 118.000s 0.000us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 13.000s 0.000us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 288.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 0.000us 1 1 100.00
dma_csr_rw 2.000s 0.000us 1 1 100.00
dma_csr_aliasing 4.000s 0.000us 1 1 100.00
dma_same_csr_outstanding 2.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 0.000us 1 1 100.00
dma_csr_rw 2.000s 0.000us 1 1 100.00
dma_csr_aliasing 4.000s 0.000us 1 1 100.00
dma_same_csr_outstanding 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 0.000us 1 1 100.00
dma_generic_stress 115.000s 0.000us 1 1 100.00
dma_handshake_stress 118.000s 0.000us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 0.000us 1 1 100.00
dma_tl_intg_err 4.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 95.000s 0.000us 1 1 100.00
dma_longer_transfer 4.000s 0.000us 1 1 100.00
dma_stress_all_with_rand_reset 15.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 86926378587635338460942874148806511481405578550915926208034127594574495634801 116
UVM_ERROR @ 682655596ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 682655596ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---