Simulation Results: i2c

 
24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.12 %
  • code
  • 81.10 %
  • assert
  • 95.98 %
  • func
  • 81.29 %
  • line
  • 96.29 %
  • branch
  • 91.98 %
  • cond
  • 84.70 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 14.130s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.660s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.770s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.690s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.070s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.730s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 1.070s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.990s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 16.320s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 3.680s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.680s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 199.170s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 91.830s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.850s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 18.710s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 8.640s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 41.090s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 10.450s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 6.000s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.910s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 537.710s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.610s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 15.110s 0.000us 1 1 100.00
i2c_target_intr_smoke 5.370s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.780s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.360s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 38.550s 0.000us 1 1 100.00
i2c_target_stress_rd 15.110s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 57.000s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.400s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 2.430s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.000s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.450s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.780s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.980s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 3.680s 0.000us 1 1 100.00
i2c_host_perf_precise 145.830s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 10.450s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.430s 0.000us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.570s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 2.110s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.390s 0.000us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.820s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.890s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.640s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.730s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.310s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.310s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.770s 0.000us 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 1.070s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.980s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.770s 0.000us 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 1.070s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.850s 0.000us 1 1 100.00
i2c_sec_cm 0.890s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.850s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 9.840s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.010s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 20.720s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 113042554041317307117443654205564549709240805012249853331839479331302037687759 94
UVM_ERROR @ 182375696 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 182375696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 18041871582218740941939644176516608619456596633530140742316656654691131396028 101
UVM_ERROR @ 1551322320 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1551322320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 90626169093420280565909154550933462310019785880781446708741340668658013290459 84
UVM_ERROR @ 813185003 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 813185003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 76666784702268170755272084138302699564901140975187118268726503890906111257286 78
UVM_ERROR @ 449730067 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 449730067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 34313685347817845560795048763998018167814022696709362360150501102308823597810 89
UVM_ERROR @ 633421227 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 633421227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
i2c_target_stress_all_with_rand_reset 45905612775422740386522311988155848325310533761853210982885497327499759401417 102
UVM_ERROR @ 7518562066 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7518562066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_mode_toggle 103456667014325283135194966572752882143696106049573723831647541097981612557054 85
UVM_ERROR @ 540378968 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @247613
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 65433982792366000883542017564739640195478081823784733410580296687718767110479 78
UVM_ERROR @ 162431829 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 162431829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---