Simulation Results: keymgr

 
24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.55 %
  • code
  • 95.27 %
  • assert
  • 97.49 %
  • func
  • 69.89 %
  • line
  • 98.74 %
  • branch
  • 97.58 %
  • cond
  • 93.65 %
  • toggle
  • 98.02 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.830s 0.000us 1 1 100.00
random 1 1 100.00
keymgr_random 7.080s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.980s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.330s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.660s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.160s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
keymgr_csr_aliasing 5.660s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.640s 0.000us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 19.670s 0.000us 1 1 100.00
keymgr_sideload_kmac 3.620s 0.000us 1 1 100.00
keymgr_sideload_aes 3.140s 0.000us 1 1 100.00
keymgr_sideload_otbn 1.920s 0.000us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.490s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.580s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.550s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.730s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 4.460s 0.000us 1 1 100.00
sync_async_fault_cross 0 1 0.00
keymgr_sync_async_fault_cross 2.270s 0.000us 0 1 0.00
stress_all 1 1 100.00
keymgr_stress_all 25.950s 0.000us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 1.020s 0.000us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.820s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.220s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.220s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.980s 0.000us 1 1 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
keymgr_csr_aliasing 5.660s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 2.730s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.980s 0.000us 1 1 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
keymgr_csr_aliasing 5.660s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 2.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 3.030s 0.000us 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.900s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.900s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.900s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.900s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.300s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.030s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.900s 0.000us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.640s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
keymgr_random 7.080s 0.000us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
keymgr_random 7.080s 0.000us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 0.850s 0.000us 1 1 100.00
keymgr_random 7.080s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.580s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.460s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.460s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 7.080s 0.000us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.850s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.120s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.580s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.120s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.120s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.120s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 17.250s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.120s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 10.460s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
keymgr_sync_async_fault_cross 94509135854612958676830379413269131746297409616254299065295383964073218664010 196
UVM_ERROR @ 61636416 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 61636416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---