Simulation Results: mbx

 
24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.00 %
  • code
  • 91.46 %
  • assert
  • 97.15 %
  • func
  • 78.40 %
  • block
  • 96.82 %
  • line
  • 96.64 %
  • branch
  • 91.71 %
  • toggle
  • 86.04 %
Validation stages
V1
87.50%
V2
81.25%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 32.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 10.000s 0.000us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 124.000s 0.000us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 34.000s 0.000us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 17.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 1.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 1.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 1.000s 0.000us 1 1 100.00
mbx_tl_intg_err 2.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 78853079907171687050661577371216732337864417388541918275351251392051543538236 318
UVM_ERROR @ 7431901134 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 7431901134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 22956979958127128425434918503588049724721725062740190272241837169983458679875 85
UVM_ERROR @ 2983522 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15964) { a_addr: 'h65072390 a_data: 'hb2a7f3c0 a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'he8 a_opcode: 'h1 a_user: 'h27412 d_param: 'h0 d_source: 'he8 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2983522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 96103353909220908542823289560618064429826416828430640431164098942257660314405 86
UVM_ERROR @ 11610139 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@18051) { a_addr: 'h4c21bdd4 a_data: 'hee8680ea a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h91 a_opcode: 'h0 a_user: 'h24e1d d_param: 'h0 d_source: 'h91 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 11610139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---