Simulation Results: otbn

 
24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.70 %
  • code
  • 95.34 %
  • assert
  • 89.59 %
  • func
  • 99.15 %
  • block
  • 99.41 %
  • line
  • 99.58 %
  • branch
  • 92.64 %
  • toggle
  • 91.72 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 0.000us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 95.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 33.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 18.000s 0.000us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 43.000s 0.000us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 67.000s 0.000us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 41.000s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 10.000s 0.000us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 0.000us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 5.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 5.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 6.000s 0.000us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 0.000us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 0.000us 1 1 100.00
otbn_urnd_err 5.000s 0.000us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 0.000us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 16.000s 0.000us 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 34.000s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 0.000us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 0.000us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 28.000s 0.000us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 28.000s 0.000us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 0.000us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 0.000us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 0.000us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 67.000s 0.000us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 12.000s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 128.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 95.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 0.000us 1 1 100.00