Simulation Results

Simulation Results: rv_dm/use_dmi_interface

24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.34 %

code
73.65 %

assert
96.16 %

func
86.20 %

line
90.16 %

branch
75.00 %

cond
75.91 %

toggle
70.95 %

FSM
56.25 %

Validation stages

V1		96.77%
V2		75.00%
V2S		100.00%
V3		0.00%
unmapped		0.00%

30/31 passed

96.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	3.330s	0.000us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.740s	0.000us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.280s	0.000us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	8.180s	0.000us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	0.970s	0.000us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	48.360s	0.000us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	7.840s	0.000us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	121.490s	0.000us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	395.380s	0.000us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	2.200s	0.000us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.070s	0.000us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	0.900s	0.000us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.970s	0.000us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	1.140s	0.000us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	2.270s	0.000us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.930s	0.000us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	0.980s	0.000us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	2.200s	0.000us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.870s	0.000us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	1.400s	0.000us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	0.900s	0.000us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	1.080s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	2.300s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	2.950s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	37.350s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	21.030s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.700s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	21.030s	0.000us	1	1	100.00
	rv_dm_csr_rw	2.950s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.850s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	1.270s	0.000us	1	1	100.00

21/28 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	3.330s	0.000us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.210s	0.000us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.840s	0.000us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	1.060s	0.000us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.720s	0.000us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	564.970s	0.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	168.720s	0.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	278.570s	0.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	587.560s	0.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.890s	0.000us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	3.590s	0.000us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.000s	0.000us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.750s	0.000us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	5.270s	0.000us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	38.030s	0.000us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.760s	0.000us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	2.430s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	1.020s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	3.340s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	3.340s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	21.030s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	2.300s	0.000us	1	1	100.00
	rv_dm_csr_rw	2.950s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	4.420s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	21.030s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	2.300s	0.000us	1	1	100.00
	rv_dm_csr_rw	2.950s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	4.420s	0.000us	1	1	100.00

V2S

12/12 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	1.730s	0.000us	1	1	100.00
	rv_dm_tl_intg_err	11.920s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	11.920s	0.000us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	3.590s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.960s	0.000us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	3.590s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.960s	0.000us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	3.330s	0.000us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	1.180s	0.000us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.810s	0.000us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.810s	0.000us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	1.180s	0.000us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	3.820s	0.000us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	50.200s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	86240195233959798558607440781076245908971389223046567300753125950897660548913	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	31299952807536740994384617426686405265435915852754829209682321885926120238488	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	25966681408821241369112598296042895519422565760674640541954545192512911837684	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	76040451983241185051430900110630470922553812245055331113007922018423297174977	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	96680338355843880879178273664662667639288568368468986053558935305327054191025	77	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	88976530688085413202137827956895257030845513207905651501648549429840751721295	77	UVM_ERROR @ 106133724 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 106133724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	65696663857804714157697519699333789349134214626751798890133064474541387952972	100	UVM_ERROR @ 2360955583 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 2360955583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	88030024984243225585710819237742419496308231172952533446512458429360532609239	77	UVM_ERROR @ 89243478 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 89243478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	79324008458041683741581088273356731749414185970441394481213695489945722465194	87	UVM_ERROR @ 341284888 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 341284888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	69217574549128392631896301698091090012766777701406471050039679454613740147919	77	UVM_ERROR @ 259853796 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (31703910 [0x1e3c366] vs 0 [0x0]) UVM_INFO @ 259853796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---