Simulation Results

Simulation Results: spi_device/1r1w

24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.98 %

code
93.30 %

assert
94.64 %

func
75.99 %

line
99.07 %

branch
98.32 %

cond
96.19 %

toggle
83.54 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		96.15%
V2S		100.00%
unmapped		100.00%

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	256.590s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.030s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.310s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	15.310s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	6.090s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	2.930s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.310s	0.000us	1	1	100.00
	spi_device_csr_aliasing	6.090s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.770s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.800s	0.000us	1	1	100.00

50/52 passed

96.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.830s	0.000us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.870s	0.000us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.720s	0.000us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	0.900s	0.000us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	0.900s	0.000us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	3.940s	0.000us	1	1	100.00
	spi_device_tpm_sts_read	1.030s	0.000us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	4.380s	0.000us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	9.200s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	2.740s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	2.740s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	6.440s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	6.440s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	6.440s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	6.440s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	6.440s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	1.820s	0.000us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	4.510s	0.000us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	4.510s	0.000us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	4.510s	0.000us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	3.520s	0.000us	1	1	100.00
	spi_device_read_buffer_direct	6.130s	0.000us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	4.510s	0.000us	1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	117.100s	0.000us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	2.380s	0.000us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	2.380s	0.000us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	256.590s	0.000us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	151.890s	0.000us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	113.950s	0.000us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.850s	0.000us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	1.030s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	4.600s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	4.600s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.030s	0.000us	1	1	100.00
	spi_device_csr_rw	1.310s	0.000us	1	1	100.00
	spi_device_csr_aliasing	6.090s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	1.730s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.030s	0.000us	1	1	100.00
	spi_device_csr_rw	1.310s	0.000us	1	1	100.00
	spi_device_csr_aliasing	6.090s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	1.730s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	13.990s	0.000us	1	1	100.00
	spi_device_sec_cm	1.250s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	13.990s	0.000us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	368.430s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	51854491763336202339615530323217293311984689998419578810024255248317572256144	76	UVM_ERROR @ 943167 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[66]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 943167 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 943167 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[962]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	87140843434283859672698949484380898630594639027614279365509043965905912509250	76	UVM_ERROR @ 3835980 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x21b6c [100001101101101100] vs 0x0 [0]) UVM_ERROR @ 3843980 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x71a729 [11100011010011100101001] vs 0x0 [0]) UVM_ERROR @ 3914980 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x755791 [11101010101011110010001] vs 0x0 [0]) UVM_ERROR @ 3966980 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xac5456 [101011000101010001010110] vs 0x0 [0]) UVM_ERROR @ 4064980 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d94bf [1011011001010010111111] vs 0x0 [0])