Simulation Results

Simulation Results: uart

24/03/2026 16:05:07 DVSim: v1.16.0 sha: bbe4dbf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.18 %

code
94.98 %

assert
97.12 %

func
51.44 %

line
98.86 %

branch
96.50 %

cond
93.00 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		97.06%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.160s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.630s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.670s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.020s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.930s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.780s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.670s	0.000us	1	1	100.00
	uart_csr_aliasing	0.930s	0.000us	1	1	100.00

33/34 passed

97.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	25.170s	0.000us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.160s	0.000us	1	1	100.00
	uart_tx_rx	25.170s	0.000us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	5.920s	0.000us	1	1	100.00
	uart_rx_parity_err	131.480s	0.000us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	25.170s	0.000us	1	1	100.00
	uart_intr	5.920s	0.000us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	9.200s	0.000us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	35.400s	0.000us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	12.270s	0.000us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	5.920s	0.000us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	5.920s	0.000us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	5.920s	0.000us	1	1	100.00
perf				1	1	100.00
	uart_perf	172.460s	0.000us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	3.500s	0.000us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	3.500s	0.000us	1	1	100.00
rx_noise_filter				1	1	100.00
	uart_noise_filter	10.850s	0.000us	1	1	100.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.940s	0.000us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.960s	0.000us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	9.800s	0.000us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	324.530s	0.000us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	1.450s	0.000us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	0.700s	0.000us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.720s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.140s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.140s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.630s	0.000us	1	1	100.00
	uart_csr_rw	0.670s	0.000us	1	1	100.00
	uart_csr_aliasing	0.930s	0.000us	1	1	100.00
	uart_same_csr_outstanding	0.890s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.630s	0.000us	1	1	100.00
	uart_csr_rw	0.670s	0.000us	1	1	100.00
	uart_csr_aliasing	0.930s	0.000us	1	1	100.00
	uart_same_csr_outstanding	0.890s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_tl_intg_err	0.850s	0.000us	1	1	100.00
	uart_sec_cm	0.810s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	0.850s	0.000us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	13.530s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *
	uart_stress_all	91108011956591694382461358522055796220786982812035439040080195663722634705178	75	UVM_ERROR @ 144278804 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 144278804 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 144278804 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 153518804 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 2 UVM_ERROR @ 153528804 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty