Simulation Results: i2c

 
25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.15 %
  • code
  • 82.07 %
  • assert
  • 96.41 %
  • func
  • 82.98 %
  • line
  • 96.60 %
  • branch
  • 92.83 %
  • cond
  • 87.22 %
  • toggle
  • 89.66 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
93.88%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 36.950s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 15.310s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.740s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.750s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.190s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.460s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.790s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.750s 0.000us 1 1 100.00
i2c_csr_aliasing 1.460s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.690s 0.000us 0 1 0.00
host_stress_all 1 1 100.00
i2c_host_stress_all 333.100s 0.000us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 332.600s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.730s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 72.830s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 38.420s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.900s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 11.240s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 2.760s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 64.050s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 22.360s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.910s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.700s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 48.690s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.710s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 19.080s 0.000us 1 1 100.00
i2c_target_intr_smoke 4.460s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.400s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 0.920s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 17.280s 0.000us 1 1 100.00
i2c_target_stress_rd 19.080s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 2.040s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.530s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.030s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.310s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.530s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.940s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.960s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 332.600s 0.000us 1 1 100.00
i2c_host_perf_precise 5.480s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 22.360s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.330s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.920s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.820s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.190s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 6.280s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.500s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.630s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.710s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.740s 0.000us 1 1 100.00
i2c_csr_rw 0.750s 0.000us 1 1 100.00
i2c_csr_aliasing 1.460s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.870s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.740s 0.000us 1 1 100.00
i2c_csr_rw 0.750s 0.000us 1 1 100.00
i2c_csr_aliasing 1.460s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.870s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.920s 0.000us 1 1 100.00
i2c_tl_intg_err 1.590s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.590s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 10.350s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.020s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 22.190s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 107104851602309361965468231346724754794830378951476850182490577299031693899620 86
UVM_ERROR @ 4107521 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 4107521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 114535982343364499849580838531863574365373228465700689687398513998509928255825 84
UVM_ERROR @ 1655401229 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1655401229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 104338750456008906787893011866782969233190557918462185084699443296528334177679 78
UVM_ERROR @ 207738556 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 207738556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 68134819477663317596782439896308904787656071027086027067096661933123972011539 92
UVM_ERROR @ 5403434437 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5403434437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 49956732509857772341826654732135004056936401042568754739448940998480003743647 95
UVM_ERROR @ 1735366609 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1735366609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 6855009323846970409430224348176991174124062097786754893283216348732563877724 87
UVM_ERROR @ 159840164 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
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