Simulation Results: kmac/masked

 
25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.52 %
  • code
  • 90.02 %
  • assert
  • 97.98 %
  • func
  • 95.56 %
  • line
  • 98.91 %
  • branch
  • 96.32 %
  • cond
  • 90.49 %
  • toggle
  • 99.59 %
  • FSM
  • 64.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 6.810s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.930s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 14.370s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.470s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.370s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.930s 0.000us 1 1 100.00
kmac_csr_aliasing 7.470s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.920s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.260s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 47.020s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 872.030s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 34.540s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 33.360s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 1056.170s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 764.940s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 1642.540s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 286.910s 0.000us 1 1 100.00
kmac_test_vectors_kmac 2.470s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 2.730s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 104.250s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 103.450s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 202.870s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 77.650s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 374.050s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.030s 0.000us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 3.750s 0.000us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 18.470s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.090s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 1.710s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.870s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 368.020s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.900s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.120s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.640s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.640s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
kmac_csr_rw 0.930s 0.000us 1 1 100.00
kmac_csr_aliasing 7.470s 0.000us 1 1 100.00
kmac_same_csr_outstanding 2.480s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
kmac_csr_rw 0.930s 0.000us 1 1 100.00
kmac_csr_aliasing 7.470s 0.000us 1 1 100.00
kmac_same_csr_outstanding 2.480s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.780s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.780s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.780s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.780s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.010s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 1.990s 0.000us 1 1 100.00
kmac_sec_cm 87.340s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 1.990s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.870s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 6.810s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 104.250s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.780s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 87.340s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 87.340s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 87.340s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 6.810s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.870s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 87.340s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 140.560s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 6.810s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 48.860s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 51889113898438978672147282503271843008201175020365930895575835530223788254928 323
UVM_ERROR @ 8667889045 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 8667889045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---