Simulation Results: rom_ctrl/32kb

 
25/03/2026 16:05:50 DVSim: v1.16.0 sha: 03992b6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 97.90 %
  • assert
  • 96.80 %
  • func
  • 97.85 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.33 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.510s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.890s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.980s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.200s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.750s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.980s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.910s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.250s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.930s 0.000us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.200s 0.000us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.070s 0.000us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.240s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.730s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.730s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.890s 0.000us 1 1 100.00
rom_ctrl_csr_rw 3.980s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.290s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.890s 0.000us 1 1 100.00
rom_ctrl_csr_rw 3.980s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.290s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.350s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 191.220s 0.000us 1 1 100.00
rom_ctrl_tl_intg_err 45.130s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 191.220s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 191.220s 0.000us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 191.220s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 191.220s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.510s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.510s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.510s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 45.130s 0.000us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
rom_ctrl_kmac_err_chk 7.070s 0.000us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.300s 0.000us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.350s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 191.220s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 295.710s 0.000us 1 1 100.00